1*4882a593SmuzhiyunROCKCHIP RK3288 LVDS/TTL VIDEO PHY WITH INNO IP BLOCK 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : "rockchip,rk3288-video-phy"; 5*4882a593Smuzhiyun - reg : the address offset of register for phy configuration. 6*4882a593Smuzhiyun - #phy-cells : must be 0. See ./phy-bindings.txt for details. 7*4882a593Smuzhiyun - clocks: must include clock specifiers corresponding to entries in the 8*4882a593Smuzhiyun clock-names property. See ../clocks/clock-bindings.txt for details. 9*4882a593Smuzhiyun - clock-names: list of clock names sorted in the same order as the clocks 10*4882a593Smuzhiyun property. Must contain "pclk". 11*4882a593Smuzhiyun - resets : Must contain an entry for each entry in reset-names. 12*4882a593Smuzhiyun See ../reset/reset.txt for details. 13*4882a593Smuzhiyun - reset-names : should be "rst". 14*4882a593Smuzhiyun - power-domains: Must contain a reference to the PM domain, if available. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun video_phy: video-phy@ff96c000 { 19*4882a593Smuzhiyun compatible = "rockchip,rk3288-video-phy"; 20*4882a593Smuzhiyun reg = <0x0 0xff96c000 0x0 0x4000>; 21*4882a593Smuzhiyun clocks = <&cru PCLK_LVDS_PHY>; 22*4882a593Smuzhiyun clock-names = "pclk"; 23*4882a593Smuzhiyun resets = <&cru SRST_LVDS_PHY>; 24*4882a593Smuzhiyun reset-names = "rst"; 25*4882a593Smuzhiyun power-domains = <&power RK3288_PD_VIO>; 26*4882a593Smuzhiyun #phy-cells = <0>; 27*4882a593Smuzhiyun status = "disabled"; 28*4882a593Smuzhiyun }; 29