1*4882a593SmuzhiyunROCKCHIP MIPI/LVDS/TTL VIDEO COMBO PHY WITH INNO IP BLOCK 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible : must be one of: 5*4882a593Smuzhiyun "rockchip,px30-video-phy", 6*4882a593Smuzhiyun "rockchip,rk3128-video-phy", 7*4882a593Smuzhiyun "rockchip,rk3368-video-phy"; 8*4882a593Smuzhiyun "rockchip,rk3568-video-phy"; 9*4882a593Smuzhiyun - reg : the address offset of register for phy and host configuration. 10*4882a593Smuzhiyun - #phy-cells : must be 0. See ./phy-bindings.txt for details. 11*4882a593Smuzhiyun - clocks: must include clock specifiers corresponding to entries in the 12*4882a593Smuzhiyun clock-names property. See ../clocks/clock-bindings.txt for details. 13*4882a593Smuzhiyun - clock-names: list of clock names sorted in the same order as the clocks 14*4882a593Smuzhiyun property. Must contain "ref", "pclk_phy", "pclk_host". 15*4882a593Smuzhiyun - #clock-cells : from common clock binding; shall be set to 0. 16*4882a593Smuzhiyun - resets : phandle to the reset of phy apb clock. 17*4882a593Smuzhiyun - reset-names : should be "rst". 18*4882a593Smuzhiyun - power-domains: Must contain a reference to the PM domain, if available. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun video_phy: video-phy@ff2e0000 { 23*4882a593Smuzhiyun compatible = "rockchip,px30-video-phy"; 24*4882a593Smuzhiyun reg = <0x0 0xff2e0000 0x0 0x10000>, 25*4882a593Smuzhiyun <0x0 0xff450000 0x0 0x10000>; 26*4882a593Smuzhiyun clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, 27*4882a593Smuzhiyun <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>; 28*4882a593Smuzhiyun clock-names = "ref", "pclk_phy", "pclk_host"; 29*4882a593Smuzhiyun #clock-cells = <0>; 30*4882a593Smuzhiyun resets = <&cru SRST_MIPIDSIPHY_P>; 31*4882a593Smuzhiyun reset-names = "rst"; 32*4882a593Smuzhiyun power-domains = <&power PX30_PD_VO>; 33*4882a593Smuzhiyun #phy-cells = <0>; 34*4882a593Smuzhiyun status = "disabled"; 35*4882a593Smuzhiyun }; 36