1ROCKCHIP MIPI/LVDS/TTL VIDEO COMBO PHY WITH INNO IP BLOCK
2
3Required properties:
4 - compatible : must be one of:
5	"rockchip,px30-video-phy",
6	"rockchip,rk3128-video-phy",
7	"rockchip,rk3368-video-phy";
8	"rockchip,rk3568-video-phy";
9 - reg : the address offset of register for phy and host configuration.
10 - #phy-cells : must be 0. See ./phy-bindings.txt for details.
11 - clocks: must include clock specifiers corresponding to entries in the
12	   clock-names property. See ../clocks/clock-bindings.txt for details.
13 - clock-names: list of clock names sorted in the same order as the clocks
14		property. Must contain "ref", "pclk_phy", "pclk_host".
15 - #clock-cells : from common clock binding; shall be set to 0.
16 - resets : phandle to the reset of phy apb clock.
17 - reset-names : should be "rst".
18 - power-domains: Must contain a reference to the PM domain, if available.
19
20Example:
21
22	video_phy: video-phy@ff2e0000 {
23		compatible = "rockchip,px30-video-phy";
24		reg = <0x0 0xff2e0000 0x0 0x10000>,
25		      <0x0 0xff450000 0x0 0x10000>;
26		clocks = <&pmucru SCLK_MIPIDSIPHY_REF>,
27			 <&cru PCLK_MIPIDSIPHY>, <&cru PCLK_MIPI_DSI>;
28		clock-names = "ref", "pclk_phy", "pclk_host";
29		#clock-cells = <0>;
30		resets = <&cru SRST_MIPIDSIPHY_P>;
31		reset-names = "rst";
32		power-domains = <&power PX30_PD_VO>;
33		#phy-cells = <0>;
34		status = "disabled";
35	};
36