1ROCKCHIP PCIE/USB3 COMBPHY WITH INNO IP BLOCK 2 3Required properties: 4 - compatible: Should be one of the listed compatibles: 5 "rockchip,rk1808-combphy" 6 - reg: Should be the address space for COMBPHY registers. 7 - #phy-cells: Should be 1. The cell number is used to select the 8 phy mode as defined in <dt-bindings/phy/phy.h>, 9 <&combphy PHY_TYPE_USB3> for USB3 PHY 10 <&combphy PHY_TYPE_PCIE> for PCIE PHY 11 - clocks: The phandle to clock provider and clock specifier pair. 12 - clock-names: Must be "refclk", the reference clock of COMBPHY. 13 - resets: The phandle to reset controller and reset specifier pair. 14 - reset-names: The string reset names, must be: 15 "otg-rst", "combphy-por", 16 "combphy-apb", "combphy-pipe". 17 - rockchip,combphygrf: The grf for COMBPHY configuration and state 18 registers. 19 20Refer to phy/phy-bindings.txt for the generic PHY binding properties. 21Optional properties: 22 - assigned-clocks: The phandle of COMBPHY reference clock. 23 - assigned-clock-rates: The COMBPHY reference clock frequency, 24 the default clock frequency is 24MHz, 25 can be set to 25000000 or 50000000. 26 27Examples: 28 29combphy_grf: syscon@fe018000 { 30 compatible = "rockchip,usb3phy-grf", "syscon"; 31 reg = <0x0 0xfe018000 0x0 0x8000>; 32}; 33 34combphy: phy@ff380000 { 35 compatible = "rockchip,rk1808-combphy"; 36 reg = <0x0 0xff380000 0x0 0x10000>; 37 #phy-cells = <1>; 38 clocks = <&cru SCLK_PCIEPHY_REF>; 39 clock-names = "refclk"; 40 assigned-clocks = <&cru SCLK_PCIEPHY_REF>; 41 assigned-clock-rates = <25000000>; 42 resets = <&cru SRST_USB3_OTG_A>, <&cru SRST_PCIEPHY_POR>, 43 <&cru SRST_PCIEPHY_P>, <&cru SRST_PCIEPHY_PIPE>; 44 reset-names = "otg-rst", "combphy-por", 45 "combphy-apb", "combphy-pipe"; 46 rockchip,combphygrf = <&combphy_grf>; 47 status = "disabled"; 48}; 49