xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/phy-mvebu.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Marvell MVEBU SATA PHY
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunPower control for the SATA phy found on Marvell MVEBU SoCs.
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunThis document extends the binding described in phy-bindings.txt
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunRequired properties :
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun - reg		   : Offset and length of the register set for the SATA device
10*4882a593Smuzhiyun - compatible	   : Should be "marvell,mvebu-sata-phy"
11*4882a593Smuzhiyun - clocks	   : phandle of clock and specifier that supplies the device
12*4882a593Smuzhiyun - clock-names	   : Should be "sata"
13*4882a593Smuzhiyun
14*4882a593SmuzhiyunExample:
15*4882a593Smuzhiyun		sata-phy@84000 {
16*4882a593Smuzhiyun			compatible = "marvell,mvebu-sata-phy";
17*4882a593Smuzhiyun			reg = <0x84000 0x0334>;
18*4882a593Smuzhiyun			clocks = <&gate_clk 15>;
19*4882a593Smuzhiyun			clock-names = "sata";
20*4882a593Smuzhiyun			#phy-cells = <0>;
21*4882a593Smuzhiyun		};
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunArmada 375 USB cluster
24*4882a593Smuzhiyun----------------------
25*4882a593Smuzhiyun
26*4882a593SmuzhiyunArmada 375 comes with an USB2 host and device controller and an USB3
27*4882a593Smuzhiyuncontroller. The USB cluster control register allows to manage common
28*4882a593Smuzhiyunfeatures of both USB controllers.
29*4882a593Smuzhiyun
30*4882a593SmuzhiyunRequired properties:
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun- compatible: "marvell,armada-375-usb-cluster"
33*4882a593Smuzhiyun- reg: Should contain usb cluster register location and length.
34*4882a593Smuzhiyun- #phy-cells : from the generic phy bindings, must be 1. Possible
35*4882a593Smuzhiyunvalues are 1 (USB2), 2 (USB3).
36*4882a593Smuzhiyun
37*4882a593SmuzhiyunExample:
38*4882a593Smuzhiyun		usbcluster: usb-cluster@18400 {
39*4882a593Smuzhiyun			compatible = "marvell,armada-375-usb-cluster";
40*4882a593Smuzhiyun			reg = <0x18400 0x4>;
41*4882a593Smuzhiyun			#phy-cells = <1>
42*4882a593Smuzhiyun		};
43