1*4882a593SmuzhiyunMediaTek Universal Flash Storage (UFS) M-PHY binding 2*4882a593Smuzhiyun-------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunUFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro. 5*4882a593SmuzhiyunEach UFS M-PHY node should have its own node. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunTo bind UFS M-PHY with UFS host controller, the controller node should 8*4882a593Smuzhiyuncontain a phandle reference to UFS M-PHY node. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties for UFS M-PHY nodes: 11*4882a593Smuzhiyun- compatible : Compatible list, contains the following controller: 12*4882a593Smuzhiyun "mediatek,mt8183-ufsphy" for ufs phy 13*4882a593Smuzhiyun persent on MT81xx chipsets. 14*4882a593Smuzhiyun- reg : Address and length of the UFS M-PHY register set. 15*4882a593Smuzhiyun- #phy-cells : This property shall be set to 0. 16*4882a593Smuzhiyun- clocks : List of phandle and clock specifier pairs. 17*4882a593Smuzhiyun- clock-names : List of clock input name strings sorted in the same 18*4882a593Smuzhiyun order as the clocks property. Following clocks are 19*4882a593Smuzhiyun mandatory. 20*4882a593Smuzhiyun "unipro": Unipro core control clock. 21*4882a593Smuzhiyun "mp": M-PHY core control clock. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun ufsphy: phy@11fa0000 { 26*4882a593Smuzhiyun compatible = "mediatek,mt8183-ufsphy"; 27*4882a593Smuzhiyun reg = <0 0x11fa0000 0 0xc000>; 28*4882a593Smuzhiyun #phy-cells = <0>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks = <&infracfg_ao INFRACFG_AO_UNIPRO_SCK_CG>, 31*4882a593Smuzhiyun <&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>; 32*4882a593Smuzhiyun clock-names = "unipro", "mp"; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun ufshci@11270000 { 36*4882a593Smuzhiyun ... 37*4882a593Smuzhiyun phys = <&ufsphy>; 38*4882a593Smuzhiyun }; 39