xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunLantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
2*4882a593Smuzhiyun===========================================
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunThis binding describes the USB PHY hardware provided by the RCU module on the
5*4882a593SmuzhiyunLantiq XWAY SoCs.
6*4882a593Smuzhiyun
7*4882a593SmuzhiyunThis node has to be a sub node of the Lantiq RCU block.
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun-------------------------------------------------------------------------------
10*4882a593SmuzhiyunRequired properties (controller (parent) node):
11*4882a593Smuzhiyun- compatible	: Should be one of
12*4882a593Smuzhiyun			"lantiq,ase-usb2-phy"
13*4882a593Smuzhiyun			"lantiq,danube-usb2-phy"
14*4882a593Smuzhiyun			"lantiq,xrx100-usb2-phy"
15*4882a593Smuzhiyun			"lantiq,xrx200-usb2-phy"
16*4882a593Smuzhiyun			"lantiq,xrx300-usb2-phy"
17*4882a593Smuzhiyun- reg		: Defines the following sets of registers in the parent
18*4882a593Smuzhiyun		  syscon device
19*4882a593Smuzhiyun			- Offset of the USB PHY configuration register
20*4882a593Smuzhiyun			- Offset of the USB Analog configuration
21*4882a593Smuzhiyun			  register (only for xrx200 and xrx200)
22*4882a593Smuzhiyun- clocks	: References to the (PMU) "phy" clk gate.
23*4882a593Smuzhiyun- clock-names	: Must be "phy"
24*4882a593Smuzhiyun- resets	: References to the RCU USB configuration reset bits.
25*4882a593Smuzhiyun- reset-names	: Must be one of the following:
26*4882a593Smuzhiyun			"phy" (optional)
27*4882a593Smuzhiyun			"ctrl" (shared)
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun-------------------------------------------------------------------------------
30*4882a593SmuzhiyunExample for the USB PHYs on an xRX200 SoC:
31*4882a593Smuzhiyun	usb_phy0: usb2-phy@18 {
32*4882a593Smuzhiyun		compatible = "lantiq,xrx200-usb2-phy";
33*4882a593Smuzhiyun		reg = <0x18 4>, <0x38 4>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		clocks = <&pmu PMU_GATE_USB0_PHY>;
36*4882a593Smuzhiyun		clock-names = "phy";
37*4882a593Smuzhiyun		resets = <&reset1 4 4>, <&reset0 4 4>;
38*4882a593Smuzhiyun		reset-names = "phy", "ctrl";
39*4882a593Smuzhiyun		#phy-cells = <0>;
40*4882a593Smuzhiyun	};
41