1*4882a593SmuzhiyunDevice tree bindings for HiSilicon INNO USB2 PHY 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be one of the following strings: 5*4882a593Smuzhiyun "hisilicon,inno-usb2-phy", 6*4882a593Smuzhiyun "hisilicon,hi3798cv200-usb2-phy". 7*4882a593Smuzhiyun- reg: Should be the address space for PHY configuration register in peripheral 8*4882a593Smuzhiyun controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC. 9*4882a593Smuzhiyun- clocks: The phandle and clock specifier pair for INNO USB2 PHY device 10*4882a593Smuzhiyun reference clock. 11*4882a593Smuzhiyun- resets: The phandle and reset specifier pair for INNO USB2 PHY device reset 12*4882a593Smuzhiyun signal. 13*4882a593Smuzhiyun- #address-cells: Must be 1. 14*4882a593Smuzhiyun- #size-cells: Must be 0. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThe INNO USB2 PHY device should be a child node of peripheral controller that 17*4882a593Smuzhiyuncontains the PHY configuration register, and each device suppports up to 2 PHY 18*4882a593Smuzhiyunports which are represented as child nodes of INNO USB2 PHY device. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunRequired properties for PHY port node: 21*4882a593Smuzhiyun- reg: The PHY port instance number. 22*4882a593Smuzhiyun- #phy-cells: Defined by generic PHY bindings. Must be 0. 23*4882a593Smuzhiyun- resets: The phandle and reset specifier pair for PHY port reset signal. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRefer to phy/phy-bindings.txt for the generic PHY binding properties 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunExample: 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunperictrl: peripheral-controller@8a20000 { 30*4882a593Smuzhiyun compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd"; 31*4882a593Smuzhiyun reg = <0x8a20000 0x1000>; 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <1>; 34*4882a593Smuzhiyun ranges = <0x0 0x8a20000 0x1000>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun usb2_phy1: usb2-phy@120 { 37*4882a593Smuzhiyun compatible = "hisilicon,hi3798cv200-usb2-phy"; 38*4882a593Smuzhiyun reg = <0x120 0x4>; 39*4882a593Smuzhiyun clocks = <&crg HISTB_USB2_PHY1_REF_CLK>; 40*4882a593Smuzhiyun resets = <&crg 0xbc 4>; 41*4882a593Smuzhiyun #address-cells = <1>; 42*4882a593Smuzhiyun #size-cells = <0>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun usb2_phy1_port0: phy@0 { 45*4882a593Smuzhiyun reg = <0>; 46*4882a593Smuzhiyun #phy-cells = <0>; 47*4882a593Smuzhiyun resets = <&crg 0xbc 8>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun usb2_phy1_port1: phy@1 { 51*4882a593Smuzhiyun reg = <1>; 52*4882a593Smuzhiyun #phy-cells = <0>; 53*4882a593Smuzhiyun resets = <&crg 0xbc 9>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun usb2_phy2: usb2-phy@124 { 58*4882a593Smuzhiyun compatible = "hisilicon,hi3798cv200-usb2-phy"; 59*4882a593Smuzhiyun reg = <0x124 0x4>; 60*4882a593Smuzhiyun clocks = <&crg HISTB_USB2_PHY2_REF_CLK>; 61*4882a593Smuzhiyun resets = <&crg 0xbc 6>; 62*4882a593Smuzhiyun #address-cells = <1>; 63*4882a593Smuzhiyun #size-cells = <0>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun usb2_phy2_port0: phy@0 { 66*4882a593Smuzhiyun reg = <0>; 67*4882a593Smuzhiyun #phy-cells = <0>; 68*4882a593Smuzhiyun resets = <&crg 0xbc 10>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun}; 72