1*4882a593Smuzhiyunmvebu armada 38x comphy driver 2*4882a593Smuzhiyun------------------------------ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis comphy controller can be found on Marvell Armada 38x. It provides a 5*4882a593Smuzhiyunnumber of shared PHYs used by various interfaces (network, sata, usb, 6*4882a593SmuzhiyunPCIe...). 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- compatible: should be "marvell,armada-380-comphy" 11*4882a593Smuzhiyun- reg: should contain the comphy register location and length. 12*4882a593Smuzhiyun- #address-cells: should be 1. 13*4882a593Smuzhiyun- #size-cells: should be 0. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- reg-names: must be "comphy" as the first name, and "conf". 18*4882a593Smuzhiyun- reg: must contain the comphy register location and length as the first 19*4882a593Smuzhiyun pair, followed by an optional configuration register address and 20*4882a593Smuzhiyun length pair. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunA sub-node is required for each comphy lane provided by the comphy. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunRequired properties (child nodes): 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- reg: comphy lane number. 27*4882a593Smuzhiyun- #phy-cells : from the generic phy bindings, must be 1. Defines the 28*4882a593Smuzhiyun input port to use for a given comphy lane. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun comphy: phy@18300 { 33*4882a593Smuzhiyun compatible = "marvell,armada-380-comphy"; 34*4882a593Smuzhiyun reg-names = "comphy", "conf"; 35*4882a593Smuzhiyun reg = <0x18300 0x100>, <0x18460 4>; 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <0>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun cpm_comphy0: phy@0 { 40*4882a593Smuzhiyun reg = <0>; 41*4882a593Smuzhiyun #phy-cells = <1>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun cpm_comphy1: phy@1 { 45*4882a593Smuzhiyun reg = <1>; 46*4882a593Smuzhiyun #phy-cells = <1>; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun }; 49