1*4882a593SmuzhiyunMixel DSI PHY for i.MX8 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Mixel MIPI-DSI PHY IP block is e.g. found on i.MX8 platforms (along the 4*4882a593SmuzhiyunMIPI-DSI IP from Northwest Logic). It represents the physical layer for the 5*4882a593Smuzhiyunelectrical signals for DSI. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: Must be: 9*4882a593Smuzhiyun - "fsl,imx8mq-mipi-dphy" 10*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 11*4882a593Smuzhiyun- clock-names: Must contain the following entries: 12*4882a593Smuzhiyun - "phy_ref": phandle and specifier referring to the DPHY ref clock 13*4882a593Smuzhiyun- reg: the register range of the PHY controller 14*4882a593Smuzhiyun- #phy-cells: number of cells in PHY, as defined in 15*4882a593Smuzhiyun Documentation/devicetree/bindings/phy/phy-bindings.txt 16*4882a593Smuzhiyun this must be <0> 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- power-domains: phandle to power domain 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun dphy: dphy@30a0030 { 23*4882a593Smuzhiyun compatible = "fsl,imx8mq-mipi-dphy"; 24*4882a593Smuzhiyun clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 25*4882a593Smuzhiyun clock-names = "phy_ref"; 26*4882a593Smuzhiyun reg = <0x30a00300 0x100>; 27*4882a593Smuzhiyun power-domains = <&pd_mipi0>; 28*4882a593Smuzhiyun #phy-cells = <0>; 29*4882a593Smuzhiyun }; 30