1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/lantiq,vrx200-pcie-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Lantiq VRX200 and ARX300 PCIe PHY Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Martin Blumenstingl <martin.blumenstingl@googlemail.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun "#phy-cells": 14*4882a593Smuzhiyun const: 1 15*4882a593Smuzhiyun description: selects the PHY mode as defined in <dt-bindings/phy/phy-lantiq-vrx200-pcie.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun enum: 19*4882a593Smuzhiyun - lantiq,vrx200-pcie-phy 20*4882a593Smuzhiyun - lantiq,arx300-pcie-phy 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun reg: 23*4882a593Smuzhiyun maxItems: 1 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - description: PHY module clock 28*4882a593Smuzhiyun - description: PDI register clock 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clock-names: 31*4882a593Smuzhiyun items: 32*4882a593Smuzhiyun - const: phy 33*4882a593Smuzhiyun - const: pdi 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun resets: 36*4882a593Smuzhiyun items: 37*4882a593Smuzhiyun - description: exclusive PHY reset line 38*4882a593Smuzhiyun - description: shared reset line between the PCIe PHY and PCIe controller 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun reset-names: 41*4882a593Smuzhiyun items: 42*4882a593Smuzhiyun - const: phy 43*4882a593Smuzhiyun - const: pcie 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun lantiq,rcu: 46*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle 47*4882a593Smuzhiyun description: phandle to the RCU syscon 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun lantiq,rcu-endian-offset: 50*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 51*4882a593Smuzhiyun description: the offset of the endian registers for this PHY instance in the RCU syscon 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun lantiq,rcu-big-endian-mask: 54*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 55*4882a593Smuzhiyun description: the mask to set the PDI (PHY) registers for this PHY instance to big endian 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun big-endian: 58*4882a593Smuzhiyun description: Configures the PDI (PHY) registers in big-endian mode 59*4882a593Smuzhiyun type: boolean 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun little-endian: 62*4882a593Smuzhiyun description: Configures the PDI (PHY) registers in big-endian mode 63*4882a593Smuzhiyun type: boolean 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunrequired: 66*4882a593Smuzhiyun - "#phy-cells" 67*4882a593Smuzhiyun - compatible 68*4882a593Smuzhiyun - reg 69*4882a593Smuzhiyun - clocks 70*4882a593Smuzhiyun - clock-names 71*4882a593Smuzhiyun - resets 72*4882a593Smuzhiyun - reset-names 73*4882a593Smuzhiyun - lantiq,rcu 74*4882a593Smuzhiyun - lantiq,rcu-endian-offset 75*4882a593Smuzhiyun - lantiq,rcu-big-endian-mask 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunadditionalProperties: false 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunexamples: 80*4882a593Smuzhiyun - | 81*4882a593Smuzhiyun pcie0_phy: phy@106800 { 82*4882a593Smuzhiyun compatible = "lantiq,vrx200-pcie-phy"; 83*4882a593Smuzhiyun reg = <0x106800 0x100>; 84*4882a593Smuzhiyun lantiq,rcu = <&rcu0>; 85*4882a593Smuzhiyun lantiq,rcu-endian-offset = <0x4c>; 86*4882a593Smuzhiyun lantiq,rcu-big-endian-mask = <0x80>; /* bit 7 */ 87*4882a593Smuzhiyun big-endian; 88*4882a593Smuzhiyun clocks = <&pmu 32>, <&pmu 36>; 89*4882a593Smuzhiyun clock-names = "phy", "pdi"; 90*4882a593Smuzhiyun resets = <&reset0 12 24>, <&reset0 22 22>; 91*4882a593Smuzhiyun reset-names = "phy", "pcie"; 92*4882a593Smuzhiyun #phy-cells = <1>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun... 96