1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Intel ComboPhy Subsystem 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Dilip Kota <eswara.kota@linux.intel.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA 14*4882a593Smuzhiyun controllers. A single Combophy provides two PHY instances. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun $nodename: 18*4882a593Smuzhiyun pattern: "combophy(@.*|-[0-9a-f])*$" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun items: 22*4882a593Smuzhiyun - const: intel,combophy-lgm 23*4882a593Smuzhiyun - const: intel,combo-phy 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun clocks: 26*4882a593Smuzhiyun maxItems: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun reg: 29*4882a593Smuzhiyun items: 30*4882a593Smuzhiyun - description: ComboPhy core registers 31*4882a593Smuzhiyun - description: PCIe app core control registers 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg-names: 34*4882a593Smuzhiyun items: 35*4882a593Smuzhiyun - const: core 36*4882a593Smuzhiyun - const: app 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun resets: 39*4882a593Smuzhiyun maxItems: 4 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun reset-names: 42*4882a593Smuzhiyun items: 43*4882a593Smuzhiyun - const: phy 44*4882a593Smuzhiyun - const: core 45*4882a593Smuzhiyun - const: iphy0 46*4882a593Smuzhiyun - const: iphy1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun intel,syscfg: 49*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle-array 50*4882a593Smuzhiyun description: Chip configuration registers handle and ComboPhy instance id 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun intel,hsio: 53*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/phandle-array 54*4882a593Smuzhiyun description: HSIO registers handle and ComboPhy instance id on NOC 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun intel,aggregation: 57*4882a593Smuzhiyun type: boolean 58*4882a593Smuzhiyun description: | 59*4882a593Smuzhiyun Specify the flag to configure ComboPHY in dual lane mode. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun intel,phy-mode: 62*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 63*4882a593Smuzhiyun description: | 64*4882a593Smuzhiyun Mode of the two phys in ComboPhy. 65*4882a593Smuzhiyun See dt-bindings/phy/phy.h for values. 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun "#phy-cells": 68*4882a593Smuzhiyun const: 1 69*4882a593Smuzhiyun 70*4882a593Smuzhiyunrequired: 71*4882a593Smuzhiyun - compatible 72*4882a593Smuzhiyun - clocks 73*4882a593Smuzhiyun - reg 74*4882a593Smuzhiyun - reg-names 75*4882a593Smuzhiyun - intel,syscfg 76*4882a593Smuzhiyun - intel,hsio 77*4882a593Smuzhiyun - intel,phy-mode 78*4882a593Smuzhiyun - "#phy-cells" 79*4882a593Smuzhiyun 80*4882a593SmuzhiyunadditionalProperties: false 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunexamples: 83*4882a593Smuzhiyun - | 84*4882a593Smuzhiyun #include <dt-bindings/phy/phy.h> 85*4882a593Smuzhiyun combophy@d0a00000 { 86*4882a593Smuzhiyun compatible = "intel,combophy-lgm", "intel,combo-phy"; 87*4882a593Smuzhiyun clocks = <&cgu0 1>; 88*4882a593Smuzhiyun #phy-cells = <1>; 89*4882a593Smuzhiyun reg = <0xd0a00000 0x40000>, 90*4882a593Smuzhiyun <0xd0a40000 0x1000>; 91*4882a593Smuzhiyun reg-names = "core", "app"; 92*4882a593Smuzhiyun resets = <&rcu0 0x50 6>, 93*4882a593Smuzhiyun <&rcu0 0x50 17>, 94*4882a593Smuzhiyun <&rcu0 0x50 23>, 95*4882a593Smuzhiyun <&rcu0 0x50 24>; 96*4882a593Smuzhiyun reset-names = "phy", "core", "iphy0", "iphy1"; 97*4882a593Smuzhiyun intel,syscfg = <&sysconf 0>; 98*4882a593Smuzhiyun intel,hsio = <&hsiol 0>; 99*4882a593Smuzhiyun intel,phy-mode = <PHY_TYPE_PCIE>; 100*4882a593Smuzhiyun intel,aggregation; 101*4882a593Smuzhiyun }; 102