1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: |+ 13*4882a593Smuzhiyun Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon 14*4882a593Smuzhiyun node is used to reference the base address of eMMC phy registers. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun The eMMC PHY node should be the child of a syscon node with the 17*4882a593Smuzhiyun required property: 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - compatible: Should be one of the following: 20*4882a593Smuzhiyun "intel,lgm-syscon", "syscon" 21*4882a593Smuzhiyun - reg: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunproperties: 25*4882a593Smuzhiyun compatible: 26*4882a593Smuzhiyun oneOf: 27*4882a593Smuzhiyun - const: intel,lgm-emmc-phy 28*4882a593Smuzhiyun - const: intel,keembay-emmc-phy 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun "#phy-cells": 31*4882a593Smuzhiyun const: 0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun reg: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks: 37*4882a593Smuzhiyun maxItems: 1 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clock-names: 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - const: emmcclk 42*4882a593Smuzhiyun 43*4882a593Smuzhiyunrequired: 44*4882a593Smuzhiyun - "#phy-cells" 45*4882a593Smuzhiyun - compatible 46*4882a593Smuzhiyun - reg 47*4882a593Smuzhiyun - clocks 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunadditionalProperties: false 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunexamples: 52*4882a593Smuzhiyun - | 53*4882a593Smuzhiyun sysconf: chiptop@e0200000 { 54*4882a593Smuzhiyun compatible = "intel,lgm-syscon", "syscon"; 55*4882a593Smuzhiyun reg = <0xe0200000 0x100>; 56*4882a593Smuzhiyun #address-cells = <1>; 57*4882a593Smuzhiyun #size-cells = <1>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun emmc_phy: emmc-phy@a8 { 60*4882a593Smuzhiyun compatible = "intel,lgm-emmc-phy"; 61*4882a593Smuzhiyun reg = <0x00a8 0x10>; 62*4882a593Smuzhiyun clocks = <&emmc>; 63*4882a593Smuzhiyun #phy-cells = <0>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun - | 68*4882a593Smuzhiyun phy@20290000 { 69*4882a593Smuzhiyun compatible = "intel,keembay-emmc-phy"; 70*4882a593Smuzhiyun reg = <0x20290000 0x54>; 71*4882a593Smuzhiyun clocks = <&emmc>; 72*4882a593Smuzhiyun clock-names = "emmcclk"; 73*4882a593Smuzhiyun #phy-cells = <0>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun... 76