1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright (c) 2020 NXP 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/phy/cdns,salvo-phy.yaml#" 6*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Cadence SALVO PHY 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Peter Chen <peter.chen@nxp.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun compatible: 15*4882a593Smuzhiyun enum: 16*4882a593Smuzhiyun - nxp,salvo-phy 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun reg: 19*4882a593Smuzhiyun maxItems: 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun clocks: 22*4882a593Smuzhiyun maxItems: 1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun clock-names: 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - const: salvo_phy_clk 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun power-domains: 29*4882a593Smuzhiyun maxItems: 1 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun "#phy-cells": 32*4882a593Smuzhiyun const: 0 33*4882a593Smuzhiyun 34*4882a593Smuzhiyunrequired: 35*4882a593Smuzhiyun - compatible 36*4882a593Smuzhiyun - reg 37*4882a593Smuzhiyun - "#phy-cells" 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunadditionalProperties: false 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunexamples: 42*4882a593Smuzhiyun - | 43*4882a593Smuzhiyun #include <dt-bindings/firmware/imx/rsrc.h> 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun usb3phy: usb3-phy@5b160000 { 46*4882a593Smuzhiyun compatible = "nxp,salvo-phy"; 47*4882a593Smuzhiyun reg = <0x5b160000 0x40000>; 48*4882a593Smuzhiyun clocks = <&usb3_lpcg 4>; 49*4882a593Smuzhiyun clock-names = "salvo_phy_clk"; 50*4882a593Smuzhiyun power-domains = <&pd IMX_SC_R_USB_2_PHY>; 51*4882a593Smuzhiyun #phy-cells = <0>; 52*4882a593Smuzhiyun }; 53