1*4882a593SmuzhiyunCadence DPHY 2*4882a593Smuzhiyun============ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunCadence DPHY block. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: should be set to "cdns,dphy". 8*4882a593Smuzhiyun- reg: physical base address and length of the DPHY registers. 9*4882a593Smuzhiyun- clocks: DPHY reference clocks. 10*4882a593Smuzhiyun- clock-names: must contain "psm" and "pll_ref". 11*4882a593Smuzhiyun- #phy-cells: must be set to 0. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun dphy0: dphy@fd0e0000{ 15*4882a593Smuzhiyun compatible = "cdns,dphy"; 16*4882a593Smuzhiyun reg = <0x0 0xfd0e0000 0x0 0x1000>; 17*4882a593Smuzhiyun clocks = <&psm_clk>, <&pll_ref_clk>; 18*4882a593Smuzhiyun clock-names = "psm", "pll_ref"; 19*4882a593Smuzhiyun #phy-cells = <0>; 20*4882a593Smuzhiyun }; 21