1*4882a593SmuzhiyunBroadcom Stingray PCIe PHY 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: must be "brcm,sr-pcie-phy" 5*4882a593Smuzhiyun- reg: base address and length of the PCIe SS register space 6*4882a593Smuzhiyun- brcm,sr-cdru: phandle to the CDRU syscon node 7*4882a593Smuzhiyun- brcm,sr-mhb: phandle to the MHB syscon node 8*4882a593Smuzhiyun- #phy-cells: Must be 1, denotes the PHY index 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunFor PAXB based root complex, one can have a configuration of up to 8 PHYs 11*4882a593SmuzhiyunPHY index goes from 0 to 7 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunFor the internal PAXC based root complex, PHY index is always 8 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun mhb: syscon@60401000 { 17*4882a593Smuzhiyun compatible = "brcm,sr-mhb", "syscon"; 18*4882a593Smuzhiyun reg = <0 0x60401000 0 0x38c>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun cdru: syscon@6641d000 { 22*4882a593Smuzhiyun compatible = "brcm,sr-cdru", "syscon"; 23*4882a593Smuzhiyun reg = <0 0x6641d000 0 0x400>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun pcie_phy: phy@40000000 { 27*4882a593Smuzhiyun compatible = "brcm,sr-pcie-phy"; 28*4882a593Smuzhiyun reg = <0 0x40000000 0 0x800>; 29*4882a593Smuzhiyun brcm,sr-cdru = <&cdru>; 30*4882a593Smuzhiyun brcm,sr-mhb = <&mhb>; 31*4882a593Smuzhiyun #phy-cells = <1>; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* users of the PCIe PHY */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun pcie0: pcie@48000000 { 37*4882a593Smuzhiyun ... 38*4882a593Smuzhiyun ... 39*4882a593Smuzhiyun phys = <&pcie_phy 0>; 40*4882a593Smuzhiyun phy-names = "pcie-phy"; 41*4882a593Smuzhiyun }; 42