1*4882a593SmuzhiyunBroadcom Cygnus PCIe PHY 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: must be "brcm,cygnus-pcie-phy" 5*4882a593Smuzhiyun- reg: base address and length of the PCIe PHY block 6*4882a593Smuzhiyun- #address-cells: must be 1 7*4882a593Smuzhiyun- #size-cells: must be 0 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunEach PCIe PHY should be represented by a child node 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties For the child node: 12*4882a593Smuzhiyun- reg: the PHY ID 13*4882a593Smuzhiyun0 - PCIe RC 0 14*4882a593Smuzhiyun1 - PCIe RC 1 15*4882a593Smuzhiyun- #phy-cells: must be 0 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun pcie_phy: phy@301d0a0 { 19*4882a593Smuzhiyun compatible = "brcm,cygnus-pcie-phy"; 20*4882a593Smuzhiyun reg = <0x0301d0a0 0x14>; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun pcie0_phy: phy@0 { 23*4882a593Smuzhiyun reg = <0>; 24*4882a593Smuzhiyun #phy-cells = <0>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun pcie1_phy: phy@1 { 28*4882a593Smuzhiyun reg = <1>; 29*4882a593Smuzhiyun #phy-cells = <0>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* users of the PCIe phy */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun pcie0: pcie@18012000 { 36*4882a593Smuzhiyun ... 37*4882a593Smuzhiyun ... 38*4882a593Smuzhiyun phys = <&pcie0_phy>; 39*4882a593Smuzhiyun phy-names = "pcie-phy"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun pcie1: pcie@18013000 { 43*4882a593Smuzhiyun ... 44*4882a593Smuzhiyun ... 45*4882a593Smuzhiyun phys = <pcie1_phy>; 46*4882a593Smuzhiyun phy-names = "pcie-phy"; 47*4882a593Smuzhiyun }; 48