1*4882a593SmuzhiyunBerlin SATA PHY 2*4882a593Smuzhiyun--------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible: should be one of 6*4882a593Smuzhiyun "marvell,berlin2-sata-phy" 7*4882a593Smuzhiyun "marvell,berlin2q-sata-phy" 8*4882a593Smuzhiyun- address-cells: should be 1 9*4882a593Smuzhiyun- size-cells: should be 0 10*4882a593Smuzhiyun- phy-cells: from the generic PHY bindings, must be 1 11*4882a593Smuzhiyun- reg: address and length of the register 12*4882a593Smuzhiyun- clocks: reference to the clock entry 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunSub-nodes: 15*4882a593SmuzhiyunEach PHY should be represented as a sub-node. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunSub-nodes required properties: 18*4882a593Smuzhiyun- reg: the PHY number 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun sata_phy: phy@f7e900a0 { 22*4882a593Smuzhiyun compatible = "marvell,berlin2q-sata-phy"; 23*4882a593Smuzhiyun reg = <0xf7e900a0 0x200>; 24*4882a593Smuzhiyun clocks = <&chip CLKID_SATA>; 25*4882a593Smuzhiyun #address-cells = <1>; 26*4882a593Smuzhiyun #size-cells = <0>; 27*4882a593Smuzhiyun #phy-cells = <1>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun sata-phy@0 { 30*4882a593Smuzhiyun reg = <0>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun sata-phy@1 { 34*4882a593Smuzhiyun reg = <1>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun }; 37