1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/allwinner,sun8i-v3s-usb-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner V3s USB PHY Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun "#phy-cells": 15*4882a593Smuzhiyun const: 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: allwinner,sun8i-v3s-usb-phy 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun items: 22*4882a593Smuzhiyun - description: PHY Control registers 23*4882a593Smuzhiyun - description: PHY PMU0 registers 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg-names: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - const: phy_ctrl 28*4882a593Smuzhiyun - const: pmu0 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun description: USB OTG PHY bus clock 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clock-names: 35*4882a593Smuzhiyun const: usb0_phy 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun resets: 38*4882a593Smuzhiyun maxItems: 1 39*4882a593Smuzhiyun description: USB OTG reset 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun reset-names: 42*4882a593Smuzhiyun const: usb0_reset 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun usb0_id_det-gpios: 45*4882a593Smuzhiyun description: GPIO to the USB OTG ID pin 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun usb0_vbus_det-gpios: 48*4882a593Smuzhiyun description: GPIO to the USB OTG VBUS detect pin 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun usb0_vbus_power-supply: 51*4882a593Smuzhiyun description: Power supply to detect the USB OTG VBUS 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun usb0_vbus-supply: 54*4882a593Smuzhiyun description: Regulator controlling USB OTG VBUS 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunrequired: 57*4882a593Smuzhiyun - "#phy-cells" 58*4882a593Smuzhiyun - compatible 59*4882a593Smuzhiyun - clocks 60*4882a593Smuzhiyun - clock-names 61*4882a593Smuzhiyun - reg 62*4882a593Smuzhiyun - reg-names 63*4882a593Smuzhiyun - resets 64*4882a593Smuzhiyun - reset-names 65*4882a593Smuzhiyun 66*4882a593SmuzhiyunadditionalProperties: false 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunexamples: 69*4882a593Smuzhiyun - | 70*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 71*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-v3s-ccu.h> 72*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-v3s-ccu.h> 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun phy@1c19400 { 75*4882a593Smuzhiyun #phy-cells = <1>; 76*4882a593Smuzhiyun compatible = "allwinner,sun8i-v3s-usb-phy"; 77*4882a593Smuzhiyun reg = <0x01c19400 0x2c>, 78*4882a593Smuzhiyun <0x01c1a800 0x4>; 79*4882a593Smuzhiyun reg-names = "phy_ctrl", 80*4882a593Smuzhiyun "pmu0"; 81*4882a593Smuzhiyun clocks = <&ccu CLK_USB_PHY0>; 82*4882a593Smuzhiyun clock-names = "usb0_phy"; 83*4882a593Smuzhiyun resets = <&ccu RST_USB_PHY0>; 84*4882a593Smuzhiyun reset-names = "usb0_reset"; 85*4882a593Smuzhiyun usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; 86*4882a593Smuzhiyun }; 87