1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/allwinner,sun8i-a83t-usb-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A83t USB PHY Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun "#phy-cells": 15*4882a593Smuzhiyun const: 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: allwinner,sun8i-a83t-usb-phy 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun items: 22*4882a593Smuzhiyun - description: PHY Control registers 23*4882a593Smuzhiyun - description: PHY PMU1 registers 24*4882a593Smuzhiyun - description: PHY PMU2 registers 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun reg-names: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - const: phy_ctrl 29*4882a593Smuzhiyun - const: pmu1 30*4882a593Smuzhiyun - const: pmu2 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clocks: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - description: USB OTG PHY bus clock 35*4882a593Smuzhiyun - description: USB Host 0 PHY bus clock 36*4882a593Smuzhiyun - description: USB Host 1 PHY bus clock 37*4882a593Smuzhiyun - description: USB HSIC 12MHz clock 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clock-names: 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - const: usb0_phy 42*4882a593Smuzhiyun - const: usb1_phy 43*4882a593Smuzhiyun - const: usb2_phy 44*4882a593Smuzhiyun - const: usb2_hsic_12M 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun resets: 47*4882a593Smuzhiyun items: 48*4882a593Smuzhiyun - description: USB OTG reset 49*4882a593Smuzhiyun - description: USB Host 1 Controller reset 50*4882a593Smuzhiyun - description: USB Host 2 Controller reset 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun reset-names: 53*4882a593Smuzhiyun items: 54*4882a593Smuzhiyun - const: usb0_reset 55*4882a593Smuzhiyun - const: usb1_reset 56*4882a593Smuzhiyun - const: usb2_reset 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun usb0_id_det-gpios: 59*4882a593Smuzhiyun description: GPIO to the USB OTG ID pin 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun usb0_vbus_det-gpios: 62*4882a593Smuzhiyun description: GPIO to the USB OTG VBUS detect pin 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun usb0_vbus_power-supply: 65*4882a593Smuzhiyun description: Power supply to detect the USB OTG VBUS 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun usb0_vbus-supply: 68*4882a593Smuzhiyun description: Regulator controlling USB OTG VBUS 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun usb1_vbus-supply: 71*4882a593Smuzhiyun description: Regulator controlling USB1 Host controller 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun usb2_vbus-supply: 74*4882a593Smuzhiyun description: Regulator controlling USB2 Host controller 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunrequired: 77*4882a593Smuzhiyun - "#phy-cells" 78*4882a593Smuzhiyun - compatible 79*4882a593Smuzhiyun - clocks 80*4882a593Smuzhiyun - clock-names 81*4882a593Smuzhiyun - reg 82*4882a593Smuzhiyun - reg-names 83*4882a593Smuzhiyun - resets 84*4882a593Smuzhiyun - reset-names 85*4882a593Smuzhiyun 86*4882a593SmuzhiyunadditionalProperties: false 87*4882a593Smuzhiyun 88*4882a593Smuzhiyunexamples: 89*4882a593Smuzhiyun - | 90*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 91*4882a593Smuzhiyun #include <dt-bindings/clock/sun8i-a83t-ccu.h> 92*4882a593Smuzhiyun #include <dt-bindings/reset/sun8i-a83t-ccu.h> 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun phy@1c19400 { 95*4882a593Smuzhiyun #phy-cells = <1>; 96*4882a593Smuzhiyun compatible = "allwinner,sun8i-a83t-usb-phy"; 97*4882a593Smuzhiyun reg = <0x01c19400 0x10>, 98*4882a593Smuzhiyun <0x01c1a800 0x14>, 99*4882a593Smuzhiyun <0x01c1b800 0x14>; 100*4882a593Smuzhiyun reg-names = "phy_ctrl", 101*4882a593Smuzhiyun "pmu1", 102*4882a593Smuzhiyun "pmu2"; 103*4882a593Smuzhiyun clocks = <&ccu CLK_USB_PHY0>, 104*4882a593Smuzhiyun <&ccu CLK_USB_PHY1>, 105*4882a593Smuzhiyun <&ccu CLK_USB_HSIC>, 106*4882a593Smuzhiyun <&ccu CLK_USB_HSIC_12M>; 107*4882a593Smuzhiyun clock-names = "usb0_phy", 108*4882a593Smuzhiyun "usb1_phy", 109*4882a593Smuzhiyun "usb2_phy", 110*4882a593Smuzhiyun "usb2_hsic_12M"; 111*4882a593Smuzhiyun resets = <&ccu RST_USB_PHY0>, 112*4882a593Smuzhiyun <&ccu RST_USB_PHY1>, 113*4882a593Smuzhiyun <&ccu RST_USB_HSIC>; 114*4882a593Smuzhiyun reset-names = "usb0_reset", 115*4882a593Smuzhiyun "usb1_reset", 116*4882a593Smuzhiyun "usb2_reset"; 117*4882a593Smuzhiyun usb0_id_det-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */ 118*4882a593Smuzhiyun usb0_vbus_power-supply = <&usb_power_supply>; 119*4882a593Smuzhiyun usb0_vbus-supply = <®_drivevbus>; 120*4882a593Smuzhiyun usb1_vbus-supply = <®_usb1_vbus>; 121*4882a593Smuzhiyun usb2_vbus-supply = <®_usb2_vbus>; 122*4882a593Smuzhiyun }; 123