1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Allwinner A13 USB PHY Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Chen-Yu Tsai <wens@csie.org> 11*4882a593Smuzhiyun - Maxime Ripard <mripard@kernel.org> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun "#phy-cells": 15*4882a593Smuzhiyun const: 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: allwinner,sun5i-a13-usb-phy 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun items: 22*4882a593Smuzhiyun - description: PHY Control registers 23*4882a593Smuzhiyun - description: PHY PMU1 registers 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg-names: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - const: phy_ctrl 28*4882a593Smuzhiyun - const: pmu1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun clocks: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun description: USB OTG PHY bus clock 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun clock-names: 35*4882a593Smuzhiyun const: usb_phy 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun resets: 38*4882a593Smuzhiyun items: 39*4882a593Smuzhiyun - description: USB OTG reset 40*4882a593Smuzhiyun - description: USB Host 1 Controller reset 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun reset-names: 43*4882a593Smuzhiyun items: 44*4882a593Smuzhiyun - const: usb0_reset 45*4882a593Smuzhiyun - const: usb1_reset 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun usb0_id_det-gpios: 48*4882a593Smuzhiyun description: GPIO to the USB OTG ID pin 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun usb0_vbus_det-gpios: 51*4882a593Smuzhiyun description: GPIO to the USB OTG VBUS detect pin 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun usb0_vbus_power-supply: 54*4882a593Smuzhiyun description: Power supply to detect the USB OTG VBUS 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun usb0_vbus-supply: 57*4882a593Smuzhiyun description: Regulator controlling USB OTG VBUS 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun usb1_vbus-supply: 60*4882a593Smuzhiyun description: Regulator controlling USB1 Host controller 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunrequired: 63*4882a593Smuzhiyun - "#phy-cells" 64*4882a593Smuzhiyun - compatible 65*4882a593Smuzhiyun - clocks 66*4882a593Smuzhiyun - clock-names 67*4882a593Smuzhiyun - reg 68*4882a593Smuzhiyun - reg-names 69*4882a593Smuzhiyun - resets 70*4882a593Smuzhiyun - reset-names 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunadditionalProperties: false 73*4882a593Smuzhiyun 74*4882a593Smuzhiyunexamples: 75*4882a593Smuzhiyun - | 76*4882a593Smuzhiyun #include <dt-bindings/gpio/gpio.h> 77*4882a593Smuzhiyun #include <dt-bindings/clock/sun5i-ccu.h> 78*4882a593Smuzhiyun #include <dt-bindings/reset/sun5i-ccu.h> 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun phy@1c13400 { 81*4882a593Smuzhiyun #phy-cells = <1>; 82*4882a593Smuzhiyun compatible = "allwinner,sun5i-a13-usb-phy"; 83*4882a593Smuzhiyun reg = <0x01c13400 0x10>, <0x01c14800 0x4>; 84*4882a593Smuzhiyun reg-names = "phy_ctrl", "pmu1"; 85*4882a593Smuzhiyun clocks = <&ccu CLK_USB_PHY0>; 86*4882a593Smuzhiyun clock-names = "usb_phy"; 87*4882a593Smuzhiyun resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; 88*4882a593Smuzhiyun reset-names = "usb0_reset", "usb1_reset"; 89*4882a593Smuzhiyun usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */ 90*4882a593Smuzhiyun usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */ 91*4882a593Smuzhiyun usb0_vbus-supply = <®_usb0_vbus>; 92*4882a593Smuzhiyun usb1_vbus-supply = <®_usb1_vbus>; 93*4882a593Smuzhiyun }; 94