1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun# Copyright 2020 Arm Ltd. 3*4882a593Smuzhiyun%YAML 1.2 4*4882a593Smuzhiyun--- 5*4882a593Smuzhiyun$id: http://devicetree.org/schemas/perf/arm,cmn.yaml# 6*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 7*4882a593Smuzhiyun 8*4882a593Smuzhiyuntitle: Arm CMN (Coherent Mesh Network) Performance Monitors 9*4882a593Smuzhiyun 10*4882a593Smuzhiyunmaintainers: 11*4882a593Smuzhiyun - Robin Murphy <robin.murphy@arm.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun compatible: 15*4882a593Smuzhiyun const: arm,cmn-600 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun reg: 18*4882a593Smuzhiyun items: 19*4882a593Smuzhiyun - description: Physical address of the base (PERIPHBASE) and 20*4882a593Smuzhiyun size (up to 64MB) of the configuration address space. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun interrupts: 23*4882a593Smuzhiyun minItems: 1 24*4882a593Smuzhiyun maxItems: 4 25*4882a593Smuzhiyun items: 26*4882a593Smuzhiyun - description: Overflow interrupt for DTC0 27*4882a593Smuzhiyun - description: Overflow interrupt for DTC1 28*4882a593Smuzhiyun - description: Overflow interrupt for DTC2 29*4882a593Smuzhiyun - description: Overflow interrupt for DTC3 30*4882a593Smuzhiyun description: One interrupt for each DTC domain implemented must 31*4882a593Smuzhiyun be specified, in order. DTC0 is always present. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun arm,root-node: 34*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 35*4882a593Smuzhiyun description: Offset from PERIPHBASE of the configuration 36*4882a593Smuzhiyun discovery node (see TRM definition of ROOTNODEBASE). 37*4882a593Smuzhiyun 38*4882a593Smuzhiyunrequired: 39*4882a593Smuzhiyun - compatible 40*4882a593Smuzhiyun - reg 41*4882a593Smuzhiyun - interrupts 42*4882a593Smuzhiyun - arm,root-node 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunadditionalProperties: false 45*4882a593Smuzhiyun 46*4882a593Smuzhiyunexamples: 47*4882a593Smuzhiyun - | 48*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 49*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/irq.h> 50*4882a593Smuzhiyun pmu@50000000 { 51*4882a593Smuzhiyun compatible = "arm,cmn-600"; 52*4882a593Smuzhiyun reg = <0x50000000 0x4000000>; 53*4882a593Smuzhiyun /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */ 54*4882a593Smuzhiyun interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 55*4882a593Smuzhiyun arm,root-node = <0x104000>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun... 58