1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Socionext UniPhier PCIe endpoint controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun UniPhier PCIe endpoint controller is based on the Synopsys DesignWare 11*4882a593Smuzhiyun PCI core. It shares common features with the PCIe DesignWare core and 12*4882a593Smuzhiyun inherits common properties defined in 13*4882a593Smuzhiyun Documentation/devicetree/bindings/pci/designware-pcie.txt. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunmaintainers: 16*4882a593Smuzhiyun - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunallOf: 19*4882a593Smuzhiyun - $ref: "pci-ep.yaml#" 20*4882a593Smuzhiyun 21*4882a593Smuzhiyunproperties: 22*4882a593Smuzhiyun compatible: 23*4882a593Smuzhiyun const: socionext,uniphier-pro5-pcie-ep 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun minItems: 4 27*4882a593Smuzhiyun maxItems: 5 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun reg-names: 30*4882a593Smuzhiyun oneOf: 31*4882a593Smuzhiyun - items: 32*4882a593Smuzhiyun - const: dbi 33*4882a593Smuzhiyun - const: dbi2 34*4882a593Smuzhiyun - const: link 35*4882a593Smuzhiyun - const: addr_space 36*4882a593Smuzhiyun - items: 37*4882a593Smuzhiyun - const: dbi 38*4882a593Smuzhiyun - const: dbi2 39*4882a593Smuzhiyun - const: link 40*4882a593Smuzhiyun - const: addr_space 41*4882a593Smuzhiyun - const: atu 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun clocks: 44*4882a593Smuzhiyun maxItems: 2 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun clock-names: 47*4882a593Smuzhiyun items: 48*4882a593Smuzhiyun - const: gio 49*4882a593Smuzhiyun - const: link 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun resets: 52*4882a593Smuzhiyun maxItems: 2 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun reset-names: 55*4882a593Smuzhiyun items: 56*4882a593Smuzhiyun - const: gio 57*4882a593Smuzhiyun - const: link 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun num-ib-windows: 60*4882a593Smuzhiyun const: 16 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun num-ob-windows: 63*4882a593Smuzhiyun const: 16 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun num-lanes: true 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun phys: 68*4882a593Smuzhiyun maxItems: 1 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun phy-names: 71*4882a593Smuzhiyun const: pcie-phy 72*4882a593Smuzhiyun 73*4882a593Smuzhiyunrequired: 74*4882a593Smuzhiyun - compatible 75*4882a593Smuzhiyun - reg 76*4882a593Smuzhiyun - reg-names 77*4882a593Smuzhiyun - clocks 78*4882a593Smuzhiyun - clock-names 79*4882a593Smuzhiyun - resets 80*4882a593Smuzhiyun - reset-names 81*4882a593Smuzhiyun 82*4882a593SmuzhiyunadditionalProperties: false 83*4882a593Smuzhiyun 84*4882a593Smuzhiyunexamples: 85*4882a593Smuzhiyun - | 86*4882a593Smuzhiyun pcie_ep: pcie-ep@66000000 { 87*4882a593Smuzhiyun compatible = "socionext,uniphier-pro5-pcie-ep"; 88*4882a593Smuzhiyun reg-names = "dbi", "dbi2", "link", "addr_space"; 89*4882a593Smuzhiyun reg = <0x66000000 0x1000>, <0x66001000 0x1000>, 90*4882a593Smuzhiyun <0x66010000 0x10000>, <0x67000000 0x400000>; 91*4882a593Smuzhiyun clock-names = "gio", "link"; 92*4882a593Smuzhiyun clocks = <&sys_clk 12>, <&sys_clk 24>; 93*4882a593Smuzhiyun reset-names = "gio", "link"; 94*4882a593Smuzhiyun resets = <&sys_rst 12>, <&sys_rst 24>; 95*4882a593Smuzhiyun num-ib-windows = <16>; 96*4882a593Smuzhiyun num-ob-windows = <16>; 97*4882a593Smuzhiyun num-lanes = <4>; 98*4882a593Smuzhiyun phy-names = "pcie-phy"; 99*4882a593Smuzhiyun phys = <&pcie_phy>; 100*4882a593Smuzhiyun }; 101