xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Mediatek/Ralink RT3883 PCI controller
2*4882a593Smuzhiyun
3*4882a593Smuzhiyun1) Main node
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun   Required properties:
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun   - compatible: must be "ralink,rt3883-pci"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun   - reg: specifies the physical base address of the controller and
10*4882a593Smuzhiyun     the length of the memory mapped region.
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun   - #address-cells: specifies the number of cells needed to encode an
13*4882a593Smuzhiyun     address. The value must be 1.
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun   - #size-cells: specifies the number of cells used to represent the size
16*4882a593Smuzhiyun     of an address. The value must be 1.
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun   - ranges: specifies the translation between child address space and parent
19*4882a593Smuzhiyun     address space
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  Optional properties:
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun   - status: indicates the operational status of the device.
24*4882a593Smuzhiyun     Value must be either "disabled" or "okay".
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun2) Child nodes
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun   The main node must have two child nodes which describes the built-in
29*4882a593Smuzhiyun   interrupt controller and the PCI host bridge.
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun   a) Interrupt controller:
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun   Required properties:
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun   - interrupt-controller: identifies the node as an interrupt controller
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun   - #address-cells: specifies the number of cells needed to encode an
38*4882a593Smuzhiyun     address. The value must be 0. As such, 'interrupt-map' nodes do not
39*4882a593Smuzhiyun     have to specify a parent unit address.
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun   - #interrupt-cells: specifies the number of cells needed to encode an
42*4882a593Smuzhiyun     interrupt source. The value must be 1.
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun   - interrupts: specifies the interrupt source of the parent interrupt
45*4882a593Smuzhiyun     controller. The format of the interrupt specifier depends on the
46*4882a593Smuzhiyun     parent interrupt controller.
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun   b) PCI host bridge:
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun   Required properties:
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun   - #address-cells: specifies the number of cells needed to encode an
53*4882a593Smuzhiyun     address. The value must be 0.
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun   - #size-cells: specifies the number of cells used to represent the size
56*4882a593Smuzhiyun     of an address. The value must be 2.
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun   - #interrupt-cells: specifies the number of cells needed to encode an
59*4882a593Smuzhiyun     interrupt source. The value must be 1.
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun   - device_type: must be "pci"
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun   - bus-range: PCI bus numbers covered
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun   - ranges: specifies the ranges for the PCI memory and I/O regions
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun   - interrupt-map-mask,
68*4882a593Smuzhiyun   - interrupt-map: standard PCI properties to define the mapping of the
69*4882a593Smuzhiyun     PCI interface to interrupt numbers.
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun   The PCI host bridge node might have additional sub-nodes representing
72*4882a593Smuzhiyun   the onboard PCI devices/PCI slots. Each such sub-node must have the
73*4882a593Smuzhiyun   following mandatory properties:
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun     - reg: used only for interrupt mapping, so only the first four bytes
76*4882a593Smuzhiyun       are used to refer to the correct bus number and device number.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun     - device_type: must be "pci"
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun   If a given sub-node represents a PCI bridge it must have following
81*4882a593Smuzhiyun   mandatory properties as well:
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun     - #address-cells: must be set to <3>
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun     - #size-cells: must set to <2>
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun     - #interrupt-cells: must be set to <1>
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun     - interrupt-map-mask,
90*4882a593Smuzhiyun     - interrupt-map: standard PCI properties to define the mapping of the
91*4882a593Smuzhiyun       PCI interface to interrupt numbers.
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun   Besides the required properties the sub-nodes may have these optional
94*4882a593Smuzhiyun   properties:
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun     - status: indicates the operational status of the sub-node.
97*4882a593Smuzhiyun       Value must be either "disabled" or "okay".
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun3) Example:
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun   a) SoC specific dtsi file:
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun	pci@10140000 {
104*4882a593Smuzhiyun		compatible = "ralink,rt3883-pci";
105*4882a593Smuzhiyun		reg = <0x10140000 0x20000>;
106*4882a593Smuzhiyun		#address-cells = <1>;
107*4882a593Smuzhiyun		#size-cells = <1>;
108*4882a593Smuzhiyun		ranges; /* direct mapping */
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun		status = "disabled";
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun		pciintc: interrupt-controller {
113*4882a593Smuzhiyun			interrupt-controller;
114*4882a593Smuzhiyun			#address-cells = <0>;
115*4882a593Smuzhiyun			#interrupt-cells = <1>;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun			interrupt-parent = <&cpuintc>;
118*4882a593Smuzhiyun			interrupts = <4>;
119*4882a593Smuzhiyun		};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun		host-bridge {
122*4882a593Smuzhiyun			#address-cells = <3>;
123*4882a593Smuzhiyun			#size-cells = <2>;
124*4882a593Smuzhiyun			#interrupt-cells = <1>;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun			device_type = "pci";
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun			bus-range = <0 255>;
129*4882a593Smuzhiyun			ranges = <
130*4882a593Smuzhiyun				0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
131*4882a593Smuzhiyun				0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
132*4882a593Smuzhiyun			>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun			interrupt-map-mask = <0xf800 0 0 7>;
135*4882a593Smuzhiyun			interrupt-map = <
136*4882a593Smuzhiyun				/* IDSEL 17 */
137*4882a593Smuzhiyun				0x8800 0 0 1 &pciintc 18
138*4882a593Smuzhiyun				0x8800 0 0 2 &pciintc 18
139*4882a593Smuzhiyun				0x8800 0 0 3 &pciintc 18
140*4882a593Smuzhiyun				0x8800 0 0 4 &pciintc 18
141*4882a593Smuzhiyun				/* IDSEL 18 */
142*4882a593Smuzhiyun				0x9000 0 0 1 &pciintc 19
143*4882a593Smuzhiyun				0x9000 0 0 2 &pciintc 19
144*4882a593Smuzhiyun				0x9000 0 0 3 &pciintc 19
145*4882a593Smuzhiyun				0x9000 0 0 4 &pciintc 19
146*4882a593Smuzhiyun			>;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun			pci-bridge@1 {
149*4882a593Smuzhiyun				reg = <0x0800 0 0 0 0>;
150*4882a593Smuzhiyun				device_type = "pci";
151*4882a593Smuzhiyun				#interrupt-cells = <1>;
152*4882a593Smuzhiyun				#address-cells = <3>;
153*4882a593Smuzhiyun				#size-cells = <2>;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun				interrupt-map-mask = <0x0 0 0 0>;
156*4882a593Smuzhiyun				interrupt-map = <0x0 0 0 0 &pciintc 20>;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun				status = "disabled";
159*4882a593Smuzhiyun			};
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun			pci-slot@17 {
162*4882a593Smuzhiyun				reg = <0x8800 0 0 0 0>;
163*4882a593Smuzhiyun				device_type = "pci";
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun				status = "disabled";
166*4882a593Smuzhiyun			};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun			pci-slot@18 {
169*4882a593Smuzhiyun				reg = <0x9000 0 0 0 0>;
170*4882a593Smuzhiyun				device_type = "pci";
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun				status = "disabled";
173*4882a593Smuzhiyun			};
174*4882a593Smuzhiyun		};
175*4882a593Smuzhiyun	};
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun   b) Board specific dts file:
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun	pci@10140000 {
180*4882a593Smuzhiyun		status = "okay";
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun		host-bridge {
183*4882a593Smuzhiyun			pci-bridge@1 {
184*4882a593Smuzhiyun				status = "okay";
185*4882a593Smuzhiyun			};
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188