1*4882a593SmuzhiyunRenesas AHB to PCI bridge 2*4882a593Smuzhiyun------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThis is the bridge used internally to connect the USB controllers to the 5*4882a593SmuzhiyunAHB. There is one bridge instance per USB port connected to the internal 6*4882a593SmuzhiyunOHCI and EHCI controllers. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC; 10*4882a593Smuzhiyun "renesas,pci-r8a7743" for the R8A7743 SoC; 11*4882a593Smuzhiyun "renesas,pci-r8a7744" for the R8A7744 SoC; 12*4882a593Smuzhiyun "renesas,pci-r8a7745" for the R8A7745 SoC; 13*4882a593Smuzhiyun "renesas,pci-r8a7790" for the R8A7790 SoC; 14*4882a593Smuzhiyun "renesas,pci-r8a7791" for the R8A7791 SoC; 15*4882a593Smuzhiyun "renesas,pci-r8a7793" for the R8A7793 SoC; 16*4882a593Smuzhiyun "renesas,pci-r8a7794" for the R8A7794 SoC; 17*4882a593Smuzhiyun "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or 18*4882a593Smuzhiyun RZ/G1 compatible device. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun When compatible with the generic version, nodes must list the 22*4882a593Smuzhiyun SoC-specific version corresponding to the platform first 23*4882a593Smuzhiyun followed by the generic version. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- reg: A list of physical regions to access the device: the first is 26*4882a593Smuzhiyun the operational registers for the OHCI/EHCI controllers and the 27*4882a593Smuzhiyun second is for the bridge configuration and control registers. 28*4882a593Smuzhiyun- interrupts: interrupt for the device. 29*4882a593Smuzhiyun- clocks: The reference to the device clock. 30*4882a593Smuzhiyun- bus-range: The PCI bus number range; as this is a single bus, the range 31*4882a593Smuzhiyun should be specified as the same value twice. 32*4882a593Smuzhiyun- #address-cells: must be 3. 33*4882a593Smuzhiyun- #size-cells: must be 2. 34*4882a593Smuzhiyun- #interrupt-cells: must be 1. 35*4882a593Smuzhiyun- interrupt-map: standard property used to define the mapping of the PCI 36*4882a593Smuzhiyun interrupts to the GIC interrupts. 37*4882a593Smuzhiyun- interrupt-map-mask: standard property that helps to define the interrupt 38*4882a593Smuzhiyun mapping. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunOptional properties: 41*4882a593Smuzhiyun- dma-ranges: a single range for the inbound memory region. If not supplied, 42*4882a593Smuzhiyun defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the 43*4882a593Smuzhiyun allowed combinations of address and size. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunExample SoC configuration: 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun pci0: pci@ee090000 { 48*4882a593Smuzhiyun compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; 49*4882a593Smuzhiyun clocks = <&mstp7_clks R8A7790_CLK_EHCI>; 50*4882a593Smuzhiyun reg = <0x0 0xee090000 0x0 0xc00>, 51*4882a593Smuzhiyun <0x0 0xee080000 0x0 0x1100>; 52*4882a593Smuzhiyun interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 53*4882a593Smuzhiyun status = "disabled"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun bus-range = <0 0>; 56*4882a593Smuzhiyun #address-cells = <3>; 57*4882a593Smuzhiyun #size-cells = <2>; 58*4882a593Smuzhiyun #interrupt-cells = <1>; 59*4882a593Smuzhiyun dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 60*4882a593Smuzhiyun interrupt-map-mask = <0xff00 0 0 0x7>; 61*4882a593Smuzhiyun interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 62*4882a593Smuzhiyun 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 63*4882a593Smuzhiyun 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun usb@1,0 { 66*4882a593Smuzhiyun reg = <0x800 0 0 0 0>; 67*4882a593Smuzhiyun phys = <&usb0 0>; 68*4882a593Smuzhiyun phy-names = "usb"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun usb@2,0 { 72*4882a593Smuzhiyun reg = <0x1000 0 0 0 0>; 73*4882a593Smuzhiyun phys = <&usb0 0>; 74*4882a593Smuzhiyun phy-names = "usb"; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593SmuzhiyunExample board setup: 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun&pci0 { 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun pinctrl-0 = <&usb0_pins>; 83*4882a593Smuzhiyun pinctrl-names = "default"; 84*4882a593Smuzhiyun}; 85