1*4882a593Smuzhiyun* Mobiveil AXI PCIe Root Port Bridge DT description 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunMobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP 4*4882a593Smuzhiyunhas up to 8 outbound and inbound windows for the address translation. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- #address-cells: Address representation for root ports, set to <3> 8*4882a593Smuzhiyun- #size-cells: Size representation for root ports, set to <2> 9*4882a593Smuzhiyun- #interrupt-cells: specifies the number of cells needed to encode an 10*4882a593Smuzhiyun interrupt source. The value must be 1. 11*4882a593Smuzhiyun- compatible: Should contain "mbvl,gpex40-pcie" 12*4882a593Smuzhiyun- reg: Should contain PCIe registers location and length 13*4882a593Smuzhiyun Mandatory: 14*4882a593Smuzhiyun "config_axi_slave": PCIe controller registers 15*4882a593Smuzhiyun "csr_axi_slave" : Bridge config registers 16*4882a593Smuzhiyun Optional: 17*4882a593Smuzhiyun "gpio_slave" : GPIO registers to control slot power 18*4882a593Smuzhiyun "apb_csr" : MSI registers 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- device_type: must be "pci" 21*4882a593Smuzhiyun- apio-wins : number of requested apio outbound windows 22*4882a593Smuzhiyun default 2 outbound windows are configured - 23*4882a593Smuzhiyun 1. Config window 24*4882a593Smuzhiyun 2. Memory window 25*4882a593Smuzhiyun- ppio-wins : number of requested ppio inbound windows 26*4882a593Smuzhiyun default 1 inbound memory window is configured. 27*4882a593Smuzhiyun- bus-range: PCI bus numbers covered 28*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 29*4882a593Smuzhiyun- #interrupt-cells: specifies the number of cells needed to encode an 30*4882a593Smuzhiyun interrupt source. The value must be 1. 31*4882a593Smuzhiyun- interrupts: The interrupt line of the PCIe controller 32*4882a593Smuzhiyun last cell of this field is set to 4 to 33*4882a593Smuzhiyun denote it as IRQ_TYPE_LEVEL_HIGH type interrupt. 34*4882a593Smuzhiyun- interrupt-map-mask, 35*4882a593Smuzhiyun interrupt-map: standard PCI properties to define the mapping of the 36*4882a593Smuzhiyun PCI interface to interrupt numbers. 37*4882a593Smuzhiyun- ranges: ranges for the PCI memory regions (I/O space region is not 38*4882a593Smuzhiyun supported by hardware) 39*4882a593Smuzhiyun Please refer to the standard PCI bus binding document for a more 40*4882a593Smuzhiyun detailed explanation 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExample: 44*4882a593Smuzhiyun++++++++ 45*4882a593Smuzhiyun pcie0: pcie@a0000000 { 46*4882a593Smuzhiyun #address-cells = <3>; 47*4882a593Smuzhiyun #size-cells = <2>; 48*4882a593Smuzhiyun compatible = "mbvl,gpex40-pcie"; 49*4882a593Smuzhiyun reg = <0xa0000000 0x00001000>, 50*4882a593Smuzhiyun <0xb0000000 0x00010000>, 51*4882a593Smuzhiyun <0xff000000 0x00200000>, 52*4882a593Smuzhiyun <0xb0010000 0x00001000>; 53*4882a593Smuzhiyun reg-names = "config_axi_slave", 54*4882a593Smuzhiyun "csr_axi_slave", 55*4882a593Smuzhiyun "gpio_slave", 56*4882a593Smuzhiyun "apb_csr"; 57*4882a593Smuzhiyun device_type = "pci"; 58*4882a593Smuzhiyun apio-wins = <2>; 59*4882a593Smuzhiyun ppio-wins = <1>; 60*4882a593Smuzhiyun bus-range = <0x00000000 0x000000ff>; 61*4882a593Smuzhiyun interrupt-controller; 62*4882a593Smuzhiyun interrupt-parent = <&gic>; 63*4882a593Smuzhiyun #interrupt-cells = <1>; 64*4882a593Smuzhiyun interrupts = < 0 89 4 >; 65*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 7>; 66*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &pci_express 0>, 67*4882a593Smuzhiyun <0 0 0 1 &pci_express 1>, 68*4882a593Smuzhiyun <0 0 0 2 &pci_express 2>, 69*4882a593Smuzhiyun <0 0 0 3 &pci_express 3>; 70*4882a593Smuzhiyun ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun }; 73