1*4882a593SmuzhiyunNXP Layerscape PCIe Gen4 controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis PCIe controller is based on the Mobiveil PCIe IP and thus inherits all 4*4882a593Smuzhiyunthe common properties defined in mobiveil-pcie.txt. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: should contain the platform identifier such as: 8*4882a593Smuzhiyun "fsl,lx2160a-pcie" 9*4882a593Smuzhiyun- reg: base addresses and lengths of the PCIe controller register blocks. 10*4882a593Smuzhiyun "csr_axi_slave": Bridge config registers 11*4882a593Smuzhiyun "config_axi_slave": PCIe controller registers 12*4882a593Smuzhiyun- interrupts: A list of interrupt outputs of the controller. Must contain an 13*4882a593Smuzhiyun entry for each entry in the interrupt-names property. 14*4882a593Smuzhiyun- interrupt-names: It could include the following entries: 15*4882a593Smuzhiyun "intr": The interrupt that is asserted for controller interrupts 16*4882a593Smuzhiyun "aer": Asserted for aer interrupt when chip support the aer interrupt with 17*4882a593Smuzhiyun none MSI/MSI-X/INTx mode,but there is interrupt line for aer. 18*4882a593Smuzhiyun "pme": Asserted for pme interrupt when chip support the pme interrupt with 19*4882a593Smuzhiyun none MSI/MSI-X/INTx mode,but there is interrupt line for pme. 20*4882a593Smuzhiyun- dma-coherent: Indicates that the hardware IP block can ensure the coherency 21*4882a593Smuzhiyun of the data transferred from/to the IP block. This can avoid the software 22*4882a593Smuzhiyun cache flush/invalid actions, and improve the performance significantly. 23*4882a593Smuzhiyun- msi-parent : See the generic MSI binding described in 24*4882a593Smuzhiyun Documentation/devicetree/bindings/interrupt-controller/msi.txt. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun pcie@3400000 { 29*4882a593Smuzhiyun compatible = "fsl,lx2160a-pcie"; 30*4882a593Smuzhiyun reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 31*4882a593Smuzhiyun 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ 32*4882a593Smuzhiyun reg-names = "csr_axi_slave", "config_axi_slave"; 33*4882a593Smuzhiyun interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 34*4882a593Smuzhiyun <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 35*4882a593Smuzhiyun <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 36*4882a593Smuzhiyun interrupt-names = "aer", "pme", "intr"; 37*4882a593Smuzhiyun #address-cells = <3>; 38*4882a593Smuzhiyun #size-cells = <2>; 39*4882a593Smuzhiyun device_type = "pci"; 40*4882a593Smuzhiyun apio-wins = <8>; 41*4882a593Smuzhiyun ppio-wins = <8>; 42*4882a593Smuzhiyun dma-coherent; 43*4882a593Smuzhiyun bus-range = <0x0 0xff>; 44*4882a593Smuzhiyun msi-parent = <&its>; 45*4882a593Smuzhiyun ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; 46*4882a593Smuzhiyun #interrupt-cells = <1>; 47*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 7>; 48*4882a593Smuzhiyun interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 49*4882a593Smuzhiyun <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 50*4882a593Smuzhiyun <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 51*4882a593Smuzhiyun <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 52*4882a593Smuzhiyun }; 53