1*4882a593SmuzhiyunFaraday Technology FTPCI100 PCI Host Bridge 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis PCI bridge is found inside that Cortina Systems Gemini SoC platform and 4*4882a593Smuzhiyunis a generic IP block from Faraday Technology. It exists in two variants: 5*4882a593Smuzhiyunplain and dual PCI. The plain version embeds a cascading interrupt controller 6*4882a593Smuzhiyuninto the host bridge. The dual version routes the interrupts to the host 7*4882a593Smuzhiyunchips interrupt controller. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe host controller appear on the PCI bus with vendor ID 0x159b (Faraday 10*4882a593SmuzhiyunTechnology) and product ID 0x4321. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunMandatory properties: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- compatible: ranging from specific to generic, should be one of 15*4882a593Smuzhiyun "cortina,gemini-pci", "faraday,ftpci100" 16*4882a593Smuzhiyun "cortina,gemini-pci-dual", "faraday,ftpci100-dual" 17*4882a593Smuzhiyun "faraday,ftpci100" 18*4882a593Smuzhiyun "faraday,ftpci100-dual" 19*4882a593Smuzhiyun- reg: memory base and size for the host bridge 20*4882a593Smuzhiyun- #address-cells: set to <3> 21*4882a593Smuzhiyun- #size-cells: set to <2> 22*4882a593Smuzhiyun- #interrupt-cells: set to <1> 23*4882a593Smuzhiyun- bus-range: set to <0x00 0xff> 24*4882a593Smuzhiyun- device_type, set to "pci" 25*4882a593Smuzhiyun- ranges: see pci.txt 26*4882a593Smuzhiyun- interrupt-map-mask: see pci.txt 27*4882a593Smuzhiyun- interrupt-map: see pci.txt 28*4882a593Smuzhiyun- dma-ranges: three ranges for the inbound memory region. The ranges must 29*4882a593Smuzhiyun be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB, 30*4882a593Smuzhiyun 128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as 31*4882a593Smuzhiyun pre-fetchable. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunOptional properties: 34*4882a593Smuzhiyun- clocks: when present, this should contain the peripheral clock (PCLK) and the 35*4882a593Smuzhiyun PCI clock (PCICLK). If these are not present, they are assumed to be 36*4882a593Smuzhiyun hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz. 37*4882a593Smuzhiyun- clock-names: when present, this should contain "PCLK" for the peripheral 38*4882a593Smuzhiyun clock and "PCICLK" for the PCI-side clock. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunMandatory subnodes: 41*4882a593Smuzhiyun- For "faraday,ftpci100" a node representing the interrupt-controller inside the 42*4882a593Smuzhiyun host bridge is mandatory. It has the following mandatory properties: 43*4882a593Smuzhiyun - interrupt: see interrupt-controller/interrupts.txt 44*4882a593Smuzhiyun - interrupt-controller: see interrupt-controller/interrupts.txt 45*4882a593Smuzhiyun - #address-cells: set to <0> 46*4882a593Smuzhiyun - #interrupt-cells: set to <1> 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunI/O space considerations: 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunThe plain variant has 128MiB of non-prefetchable memory space, whereas the 51*4882a593Smuzhiyun"dual" variant has 64MiB. Take this into account when describing the ranges. 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunInterrupt map considerations: 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunThe "dual" variant will get INT A, B, C, D from the system interrupt controller 56*4882a593Smuzhiyunand should point to respective interrupt in that controller in its 57*4882a593Smuzhiyuninterrupt-map. 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunThe code which is the only documentation of how the Faraday PCI (the non-dual 60*4882a593Smuzhiyunvariant) interrupts assigns the default interrupt mapping/swizzling has 61*4882a593Smuzhiyuntypically been like this, doing the swizzling on the interrupt controller side 62*4882a593Smuzhiyunrather than in the interconnect: 63*4882a593Smuzhiyun 64*4882a593Smuzhiyuninterrupt-map-mask = <0xf800 0 0 7>; 65*4882a593Smuzhiyuninterrupt-map = 66*4882a593Smuzhiyun <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 67*4882a593Smuzhiyun <0x4800 0 0 2 &pci_intc 1>, 68*4882a593Smuzhiyun <0x4800 0 0 3 &pci_intc 2>, 69*4882a593Smuzhiyun <0x4800 0 0 4 &pci_intc 3>, 70*4882a593Smuzhiyun <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 71*4882a593Smuzhiyun <0x5000 0 0 2 &pci_intc 2>, 72*4882a593Smuzhiyun <0x5000 0 0 3 &pci_intc 3>, 73*4882a593Smuzhiyun <0x5000 0 0 4 &pci_intc 0>, 74*4882a593Smuzhiyun <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 75*4882a593Smuzhiyun <0x5800 0 0 2 &pci_intc 3>, 76*4882a593Smuzhiyun <0x5800 0 0 3 &pci_intc 0>, 77*4882a593Smuzhiyun <0x5800 0 0 4 &pci_intc 1>, 78*4882a593Smuzhiyun <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 79*4882a593Smuzhiyun <0x6000 0 0 2 &pci_intc 0>, 80*4882a593Smuzhiyun <0x6000 0 0 3 &pci_intc 1>, 81*4882a593Smuzhiyun <0x6000 0 0 4 &pci_intc 2>; 82*4882a593Smuzhiyun 83*4882a593SmuzhiyunExample: 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunpci@50000000 { 86*4882a593Smuzhiyun compatible = "cortina,gemini-pci", "faraday,ftpci100"; 87*4882a593Smuzhiyun reg = <0x50000000 0x100>; 88*4882a593Smuzhiyun interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */ 89*4882a593Smuzhiyun <26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */ 90*4882a593Smuzhiyun <27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */ 91*4882a593Smuzhiyun <28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */ 92*4882a593Smuzhiyun #address-cells = <3>; 93*4882a593Smuzhiyun #size-cells = <2>; 94*4882a593Smuzhiyun #interrupt-cells = <1>; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun bus-range = <0x00 0xff>; 97*4882a593Smuzhiyun ranges = /* 1MiB I/O space 0x50000000-0x500fffff */ 98*4882a593Smuzhiyun <0x01000000 0 0 0x50000000 0 0x00100000>, 99*4882a593Smuzhiyun /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */ 100*4882a593Smuzhiyun <0x02000000 0 0x58000000 0x58000000 0 0x08000000>; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun /* DMA ranges */ 103*4882a593Smuzhiyun dma-ranges = 104*4882a593Smuzhiyun /* 128MiB at 0x00000000-0x07ffffff */ 105*4882a593Smuzhiyun <0x02000000 0 0x00000000 0x00000000 0 0x08000000>, 106*4882a593Smuzhiyun /* 64MiB at 0x00000000-0x03ffffff */ 107*4882a593Smuzhiyun <0x02000000 0 0x00000000 0x00000000 0 0x04000000>, 108*4882a593Smuzhiyun /* 64MiB at 0x00000000-0x03ffffff */ 109*4882a593Smuzhiyun <0x02000000 0 0x00000000 0x00000000 0 0x04000000>; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0 0 7>; 112*4882a593Smuzhiyun interrupt-map = 113*4882a593Smuzhiyun <0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */ 114*4882a593Smuzhiyun <0x4800 0 0 2 &pci_intc 1>, 115*4882a593Smuzhiyun <0x4800 0 0 3 &pci_intc 2>, 116*4882a593Smuzhiyun <0x4800 0 0 4 &pci_intc 3>, 117*4882a593Smuzhiyun <0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */ 118*4882a593Smuzhiyun <0x5000 0 0 2 &pci_intc 2>, 119*4882a593Smuzhiyun <0x5000 0 0 3 &pci_intc 3>, 120*4882a593Smuzhiyun <0x5000 0 0 4 &pci_intc 0>, 121*4882a593Smuzhiyun <0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */ 122*4882a593Smuzhiyun <0x5800 0 0 2 &pci_intc 3>, 123*4882a593Smuzhiyun <0x5800 0 0 3 &pci_intc 0>, 124*4882a593Smuzhiyun <0x5800 0 0 4 &pci_intc 1>, 125*4882a593Smuzhiyun <0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */ 126*4882a593Smuzhiyun <0x6000 0 0 2 &pci_intc 0>, 127*4882a593Smuzhiyun <0x6000 0 0 3 &pci_intc 0>, 128*4882a593Smuzhiyun <0x6000 0 0 4 &pci_intc 0>; 129*4882a593Smuzhiyun pci_intc: interrupt-controller { 130*4882a593Smuzhiyun interrupt-parent = <&intcon>; 131*4882a593Smuzhiyun interrupt-controller; 132*4882a593Smuzhiyun #address-cells = <0>; 133*4882a593Smuzhiyun #interrupt-cells = <1>; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun}; 136