1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Cadence PCIe Host 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Tom Joseph <tjoseph@cadence.com> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "/schemas/pci/pci-bus.yaml#" 14*4882a593Smuzhiyun - $ref: "cdns-pcie.yaml#" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun cdns,max-outbound-regions: 18*4882a593Smuzhiyun description: maximum number of outbound regions 19*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 20*4882a593Smuzhiyun minimum: 1 21*4882a593Smuzhiyun maximum: 32 22*4882a593Smuzhiyun default: 32 23*4882a593Smuzhiyun deprecated: true 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun cdns,no-bar-match-nbits: 26*4882a593Smuzhiyun description: 27*4882a593Smuzhiyun Set into the no BAR match register to configure the number of least 28*4882a593Smuzhiyun significant bits kept during inbound (PCIe -> AXI) address translations 29*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 30*4882a593Smuzhiyun minimum: 0 31*4882a593Smuzhiyun maximum: 64 32*4882a593Smuzhiyun default: 32 33*4882a593Smuzhiyun deprecated: true 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun msi-parent: true 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunadditionalProperties: true 38