1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pci/cdns,cdns-pcie-host.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Cadence PCIe host controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Tom Joseph <tjoseph@cadence.com> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: /schemas/pci/pci-bus.yaml# 14*4882a593Smuzhiyun - $ref: "cdns-pcie-host.yaml#" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: cdns,cdns-pcie-host 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 2 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg-names: 24*4882a593Smuzhiyun items: 25*4882a593Smuzhiyun - const: reg 26*4882a593Smuzhiyun - const: cfg 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun msi-parent: true 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunrequired: 31*4882a593Smuzhiyun - reg 32*4882a593Smuzhiyun - reg-names 33*4882a593Smuzhiyun 34*4882a593SmuzhiyununevaluatedProperties: false 35*4882a593Smuzhiyun 36*4882a593Smuzhiyunexamples: 37*4882a593Smuzhiyun - | 38*4882a593Smuzhiyun bus { 39*4882a593Smuzhiyun #address-cells = <2>; 40*4882a593Smuzhiyun #size-cells = <2>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun pcie@fb000000 { 43*4882a593Smuzhiyun compatible = "cdns,cdns-pcie-host"; 44*4882a593Smuzhiyun device_type = "pci"; 45*4882a593Smuzhiyun #address-cells = <3>; 46*4882a593Smuzhiyun #size-cells = <2>; 47*4882a593Smuzhiyun bus-range = <0x0 0xff>; 48*4882a593Smuzhiyun linux,pci-domain = <0>; 49*4882a593Smuzhiyun vendor-id = <0x17cd>; 50*4882a593Smuzhiyun device-id = <0x0200>; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun reg = <0x0 0xfb000000 0x0 0x01000000>, 53*4882a593Smuzhiyun <0x0 0x41000000 0x0 0x00001000>; 54*4882a593Smuzhiyun reg-names = "reg", "cfg"; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>, 57*4882a593Smuzhiyun <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>; 58*4882a593Smuzhiyun dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x1 0x00000000>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #interrupt-cells = <0x1>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 14 0x1>, 63*4882a593Smuzhiyun <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 15 0x1>, 64*4882a593Smuzhiyun <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 16 0x1>, 65*4882a593Smuzhiyun <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 17 0x1>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun interrupt-map-mask = <0x0 0x0 0x0 0x7>; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun msi-parent = <&its_pci>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun phys = <&pcie_phy0>; 72*4882a593Smuzhiyun phy-names = "pcie-phy"; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun... 76