1*4882a593SmuzhiyunAmlogic Meson AXG DWC PCIE SoC controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunAmlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. 4*4882a593SmuzhiyunIt shares common functions with the PCIe DesignWare core driver and 5*4882a593Smuzhiyuninherits common properties defined in 6*4882a593SmuzhiyunDocumentation/devicetree/bindings/pci/designware-pcie.txt. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunAdditional properties are described here: 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: 12*4882a593Smuzhiyun should contain : 13*4882a593Smuzhiyun - "amlogic,axg-pcie" for AXG SoC Family 14*4882a593Smuzhiyun - "amlogic,g12a-pcie" for G12A SoC Family 15*4882a593Smuzhiyun to identify the core. 16*4882a593Smuzhiyun- reg: 17*4882a593Smuzhiyun should contain the configuration address space. 18*4882a593Smuzhiyun- reg-names: Must be 19*4882a593Smuzhiyun - "elbi" External local bus interface registers 20*4882a593Smuzhiyun - "cfg" Meson specific registers 21*4882a593Smuzhiyun - "config" PCIe configuration space 22*4882a593Smuzhiyun- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal. 23*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 24*4882a593Smuzhiyun- clock-names: Must include the following entries: 25*4882a593Smuzhiyun - "pclk" PCIe GEN 100M PLL clock 26*4882a593Smuzhiyun - "port" PCIe_x(A or B) RC clock gate 27*4882a593Smuzhiyun - "general" PCIe Phy clock 28*4882a593Smuzhiyun- resets: phandle to the reset lines. 29*4882a593Smuzhiyun- reset-names: must contain "port" and "apb" 30*4882a593Smuzhiyun - "port" Port A or B reset 31*4882a593Smuzhiyun - "apb" Share APB reset 32*4882a593Smuzhiyun- phys: should contain a phandle to the PCIE phy 33*4882a593Smuzhiyun- phy-names: must contain "pcie" 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun- device_type: 36*4882a593Smuzhiyun should be "pci". As specified in designware-pcie.txt 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunExample configuration: 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun pcie: pcie@f9800000 { 42*4882a593Smuzhiyun compatible = "amlogic,axg-pcie", "snps,dw-pcie"; 43*4882a593Smuzhiyun reg = <0x0 0xf9800000 0x0 0x400000 44*4882a593Smuzhiyun 0x0 0xff646000 0x0 0x2000 45*4882a593Smuzhiyun 0x0 0xf9f00000 0x0 0x100000>; 46*4882a593Smuzhiyun reg-names = "elbi", "cfg", "config"; 47*4882a593Smuzhiyun reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>; 48*4882a593Smuzhiyun interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>; 49*4882a593Smuzhiyun #interrupt-cells = <1>; 50*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 0>; 51*4882a593Smuzhiyun interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 52*4882a593Smuzhiyun bus-range = <0x0 0xff>; 53*4882a593Smuzhiyun #address-cells = <3>; 54*4882a593Smuzhiyun #size-cells = <2>; 55*4882a593Smuzhiyun device_type = "pci"; 56*4882a593Smuzhiyun ranges = <0x82000000 0 0 0x0 0xf9c00000 0 0x00300000>; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun clocks = <&clkc CLKID_USB 59*4882a593Smuzhiyun &clkc CLKID_PCIE_A 60*4882a593Smuzhiyun &clkc CLKID_PCIE_CML_EN0>; 61*4882a593Smuzhiyun clock-names = "general", 62*4882a593Smuzhiyun "pclk", 63*4882a593Smuzhiyun "port"; 64*4882a593Smuzhiyun resets = <&reset RESET_PCIE_A>, 65*4882a593Smuzhiyun <&reset RESET_PCIE_APB>; 66*4882a593Smuzhiyun reset-names = "port", 67*4882a593Smuzhiyun "apb"; 68*4882a593Smuzhiyun phys = <&pcie_phy>; 69*4882a593Smuzhiyun phy-names = "pcie"; 70*4882a593Smuzhiyun }; 71