1*4882a593Smuzhiyun* Altera PCIe controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0" 5*4882a593Smuzhiyun- reg: a list of physical base address and length for TXS and CRA. 6*4882a593Smuzhiyun For "altr,pcie-root-port-2.0", additional HIP base address and length. 7*4882a593Smuzhiyun- reg-names: must include the following entries: 8*4882a593Smuzhiyun "Txs": TX slave port region 9*4882a593Smuzhiyun "Cra": Control register access region 10*4882a593Smuzhiyun "Hip": Hard IP region (if "altr,pcie-root-port-2.0") 11*4882a593Smuzhiyun- interrupts: specifies the interrupt source of the parent interrupt 12*4882a593Smuzhiyun controller. The format of the interrupt specifier depends 13*4882a593Smuzhiyun on the parent interrupt controller. 14*4882a593Smuzhiyun- device_type: must be "pci" 15*4882a593Smuzhiyun- #address-cells: set to <3> 16*4882a593Smuzhiyun- #size-cells: set to <2> 17*4882a593Smuzhiyun- #interrupt-cells: set to <1> 18*4882a593Smuzhiyun- ranges: describes the translation of addresses for root ports and 19*4882a593Smuzhiyun standard PCI regions. 20*4882a593Smuzhiyun- interrupt-map-mask and interrupt-map: standard PCI properties to define the 21*4882a593Smuzhiyun mapping of the PCIe interface to interrupt numbers. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties: 24*4882a593Smuzhiyun- msi-parent: Link to the hardware entity that serves as the MSI controller 25*4882a593Smuzhiyun for this PCIe controller. 26*4882a593Smuzhiyun- bus-range: PCI bus numbers covered 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample 29*4882a593Smuzhiyun pcie_0: pcie@c00000000 { 30*4882a593Smuzhiyun compatible = "altr,pcie-root-port-1.0"; 31*4882a593Smuzhiyun reg = <0xc0000000 0x20000000>, 32*4882a593Smuzhiyun <0xff220000 0x00004000>; 33*4882a593Smuzhiyun reg-names = "Txs", "Cra"; 34*4882a593Smuzhiyun interrupt-parent = <&hps_0_arm_gic_0>; 35*4882a593Smuzhiyun interrupts = <0 40 4>; 36*4882a593Smuzhiyun interrupt-controller; 37*4882a593Smuzhiyun #interrupt-cells = <1>; 38*4882a593Smuzhiyun bus-range = <0x0 0xFF>; 39*4882a593Smuzhiyun device_type = "pci"; 40*4882a593Smuzhiyun msi-parent = <&msi_to_gic_gen_0>; 41*4882a593Smuzhiyun #address-cells = <3>; 42*4882a593Smuzhiyun #size-cells = <2>; 43*4882a593Smuzhiyun interrupt-map-mask = <0 0 0 7>; 44*4882a593Smuzhiyun interrupt-map = <0 0 0 1 &pcie_0 1>, 45*4882a593Smuzhiyun <0 0 0 2 &pcie_0 2>, 46*4882a593Smuzhiyun <0 0 0 3 &pcie_0 3>, 47*4882a593Smuzhiyun <0 0 0 4 &pcie_0 4>; 48*4882a593Smuzhiyun ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000 49*4882a593Smuzhiyun 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; 50*4882a593Smuzhiyun }; 51