1*4882a593Smuzhiyun* Freescale 83xx and 512x PCI bridges 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunFreescale 83xx and 512x SOCs include the same PCI bridge core. 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun83xx/512x specific notes: 6*4882a593Smuzhiyun- reg: should contain two address length tuples 7*4882a593Smuzhiyun The first is for the internal PCI bridge registers 8*4882a593Smuzhiyun The second is for the PCI config space access registers 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunExample (MPC8313ERDB) 11*4882a593Smuzhiyun pci0: pci@e0008500 { 12*4882a593Smuzhiyun interrupt-map-mask = <0xf800 0x0 0x0 0x7>; 13*4882a593Smuzhiyun interrupt-map = < 14*4882a593Smuzhiyun /* IDSEL 0x0E -mini PCI */ 15*4882a593Smuzhiyun 0x7000 0x0 0x0 0x1 &ipic 18 0x8 16*4882a593Smuzhiyun 0x7000 0x0 0x0 0x2 &ipic 18 0x8 17*4882a593Smuzhiyun 0x7000 0x0 0x0 0x3 &ipic 18 0x8 18*4882a593Smuzhiyun 0x7000 0x0 0x0 0x4 &ipic 18 0x8 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* IDSEL 0x0F - PCI slot */ 21*4882a593Smuzhiyun 0x7800 0x0 0x0 0x1 &ipic 17 0x8 22*4882a593Smuzhiyun 0x7800 0x0 0x0 0x2 &ipic 18 0x8 23*4882a593Smuzhiyun 0x7800 0x0 0x0 0x3 &ipic 17 0x8 24*4882a593Smuzhiyun 0x7800 0x0 0x0 0x4 &ipic 18 0x8>; 25*4882a593Smuzhiyun interrupt-parent = <&ipic>; 26*4882a593Smuzhiyun interrupts = <66 0x8>; 27*4882a593Smuzhiyun bus-range = <0x0 0x0>; 28*4882a593Smuzhiyun ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 29*4882a593Smuzhiyun 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 30*4882a593Smuzhiyun 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>; 31*4882a593Smuzhiyun clock-frequency = <66666666>; 32*4882a593Smuzhiyun #interrupt-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <2>; 34*4882a593Smuzhiyun #address-cells = <3>; 35*4882a593Smuzhiyun reg = <0xe0008500 0x100 /* internal registers */ 36*4882a593Smuzhiyun 0xe0008300 0x8>; /* config space access registers */ 37*4882a593Smuzhiyun compatible = "fsl,mpc8349-pci"; 38*4882a593Smuzhiyun device_type = "pci"; 39*4882a593Smuzhiyun }; 40