1*4882a593SmuzhiyunRockchip internal OTP (One Time Programmable) memory device tree bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be one of the following. 5*4882a593Smuzhiyun - "rockchip,px30-otp" - for PX30 SoCs. 6*4882a593Smuzhiyun - "rockchip,rk3308-otp" - for RK3308 SoCs. 7*4882a593Smuzhiyun- reg: Should contain the registers location and size 8*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 9*4882a593Smuzhiyun- clock-names: Should be "otp", "apb_pclk" and "phy". 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunOptional properties: 12*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 13*4882a593Smuzhiyun See ../../reset/reset.txt for details. 14*4882a593Smuzhiyun- reset-names: Should be "phy". 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunSee nvmem.txt for more information. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun otp: otp@ff290000 { 20*4882a593Smuzhiyun compatible = "rockchip,px30-otp"; 21*4882a593Smuzhiyun reg = <0x0 0xff290000 0x0 0x4000>; 22*4882a593Smuzhiyun #address-cells = <1>; 23*4882a593Smuzhiyun #size-cells = <1>; 24*4882a593Smuzhiyun clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 25*4882a593Smuzhiyun <&cru PCLK_OTP_PHY>; 26*4882a593Smuzhiyun clock-names = "otp", "apb_pclk", "phy"; 27*4882a593Smuzhiyun }; 28