1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/nvmem/qcom,qfprom.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Technologies Inc, QFPROM Efuse bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Srinivas Kandagatla <srinivas.kandagatla@linaro.org> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "nvmem.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun const: qcom,qfprom 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun reg: 20*4882a593Smuzhiyun # If the QFPROM is read-only OS image then only the corrected region 21*4882a593Smuzhiyun # needs to be provided. If the QFPROM is writable then all 4 regions 22*4882a593Smuzhiyun # must be provided. 23*4882a593Smuzhiyun oneOf: 24*4882a593Smuzhiyun - items: 25*4882a593Smuzhiyun - description: The corrected region. 26*4882a593Smuzhiyun - items: 27*4882a593Smuzhiyun - description: The corrected region. 28*4882a593Smuzhiyun - description: The raw region. 29*4882a593Smuzhiyun - description: The config region. 30*4882a593Smuzhiyun - description: The security control region. 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun # Clock must be provided if QFPROM is writable from the OS image. 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun clock-names: 36*4882a593Smuzhiyun const: core 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun # Supply reference must be provided if QFPROM is writable from the OS image. 39*4882a593Smuzhiyun vcc-supply: 40*4882a593Smuzhiyun description: Our power supply. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun # Needed if any child nodes are present. 43*4882a593Smuzhiyun "#address-cells": 44*4882a593Smuzhiyun const: 1 45*4882a593Smuzhiyun "#size-cells": 46*4882a593Smuzhiyun const: 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyunrequired: 49*4882a593Smuzhiyun - compatible 50*4882a593Smuzhiyun - reg 51*4882a593Smuzhiyun 52*4882a593SmuzhiyununevaluatedProperties: false 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunexamples: 55*4882a593Smuzhiyun - | 56*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,gcc-sc7180.h> 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun soc { 59*4882a593Smuzhiyun #address-cells = <2>; 60*4882a593Smuzhiyun #size-cells = <2>; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun efuse@784000 { 63*4882a593Smuzhiyun compatible = "qcom,qfprom"; 64*4882a593Smuzhiyun reg = <0 0x00784000 0 0x8ff>, 65*4882a593Smuzhiyun <0 0x00780000 0 0x7a0>, 66*4882a593Smuzhiyun <0 0x00782000 0 0x100>, 67*4882a593Smuzhiyun <0 0x00786000 0 0x1fff>; 68*4882a593Smuzhiyun clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 69*4882a593Smuzhiyun clock-names = "core"; 70*4882a593Smuzhiyun #address-cells = <1>; 71*4882a593Smuzhiyun #size-cells = <1>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun vcc-supply = <&vreg_l11a_1p8>; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun hstx-trim-primary@25b { 76*4882a593Smuzhiyun reg = <0x25b 0x1>; 77*4882a593Smuzhiyun bits = <1 3>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun - | 83*4882a593Smuzhiyun soc { 84*4882a593Smuzhiyun #address-cells = <2>; 85*4882a593Smuzhiyun #size-cells = <2>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun efuse@784000 { 88*4882a593Smuzhiyun compatible = "qcom,qfprom"; 89*4882a593Smuzhiyun reg = <0 0x00784000 0 0x8ff>; 90*4882a593Smuzhiyun #address-cells = <1>; 91*4882a593Smuzhiyun #size-cells = <1>; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun hstx-trim-primary@1eb { 94*4882a593Smuzhiyun reg = <0x1eb 0x1>; 95*4882a593Smuzhiyun bits = <1 4>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99