1*4882a593Smuzhiyun* Nios II Processor Binding 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding specifies what properties available in the device tree 4*4882a593Smuzhiyunrepresentation of a Nios II Processor Core. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunUsers can use sopc2dts tool for generating device tree sources (dts) from a 7*4882a593SmuzhiyunQsys system. See more detail in: http://www.alterawiki.com/wiki/Sopc2dts 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- compatible: Compatible property value should be "altr,nios2-1.0". 12*4882a593Smuzhiyun- reg: Contains CPU index. 13*4882a593Smuzhiyun- interrupt-controller: Specifies that the node is an interrupt controller 14*4882a593Smuzhiyun- #interrupt-cells: Specifies the number of cells needed to encode an 15*4882a593Smuzhiyun interrupt source, should be 1. 16*4882a593Smuzhiyun- clock-frequency: Contains the clock frequency for CPU, in Hz. 17*4882a593Smuzhiyun- dcache-line-size: Contains data cache line size. 18*4882a593Smuzhiyun- icache-line-size: Contains instruction line size. 19*4882a593Smuzhiyun- dcache-size: Contains data cache size. 20*4882a593Smuzhiyun- icache-size: Contains instruction cache size. 21*4882a593Smuzhiyun- altr,pid-num-bits: Specifies the number of bits to use to represent the process 22*4882a593Smuzhiyun identifier (PID). 23*4882a593Smuzhiyun- altr,tlb-num-ways: Specifies the number of set-associativity ways in the TLB. 24*4882a593Smuzhiyun- altr,tlb-num-entries: Specifies the number of entries in the TLB. 25*4882a593Smuzhiyun- altr,tlb-ptr-sz: Specifies size of TLB pointer. 26*4882a593Smuzhiyun- altr,has-mul: Specifies CPU hardware multipy support, should be 1. 27*4882a593Smuzhiyun- altr,has-mmu: Specifies CPU support MMU support, should be 1. 28*4882a593Smuzhiyun- altr,has-initda: Specifies CPU support initda instruction, should be 1. 29*4882a593Smuzhiyun- altr,reset-addr: Specifies CPU reset address 30*4882a593Smuzhiyun- altr,fast-tlb-miss-addr: Specifies CPU fast TLB miss exception address 31*4882a593Smuzhiyun- altr,exception-addr: Specifies CPU exception address 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunOptional properties: 34*4882a593Smuzhiyun- altr,has-div: Specifies CPU hardware divide support 35*4882a593Smuzhiyun- altr,implementation: Nios II core implementation, this should be "fast"; 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExample: 38*4882a593Smuzhiyun 39*4882a593Smuzhiyuncpu@0 { 40*4882a593Smuzhiyun device_type = "cpu"; 41*4882a593Smuzhiyun compatible = "altr,nios2-1.0"; 42*4882a593Smuzhiyun reg = <0>; 43*4882a593Smuzhiyun interrupt-controller; 44*4882a593Smuzhiyun #interrupt-cells = <1>; 45*4882a593Smuzhiyun clock-frequency = <125000000>; 46*4882a593Smuzhiyun dcache-line-size = <32>; 47*4882a593Smuzhiyun icache-line-size = <32>; 48*4882a593Smuzhiyun dcache-size = <32768>; 49*4882a593Smuzhiyun icache-size = <32768>; 50*4882a593Smuzhiyun altr,implementation = "fast"; 51*4882a593Smuzhiyun altr,pid-num-bits = <8>; 52*4882a593Smuzhiyun altr,tlb-num-ways = <16>; 53*4882a593Smuzhiyun altr,tlb-num-entries = <128>; 54*4882a593Smuzhiyun altr,tlb-ptr-sz = <7>; 55*4882a593Smuzhiyun altr,has-div = <1>; 56*4882a593Smuzhiyun altr,has-mul = <1>; 57*4882a593Smuzhiyun altr,reset-addr = <0xc2800000>; 58*4882a593Smuzhiyun altr,fast-tlb-miss-addr = <0xc7fff400>; 59*4882a593Smuzhiyun altr,exception-addr = <0xd0000020>; 60*4882a593Smuzhiyun altr,has-initda = <1>; 61*4882a593Smuzhiyun altr,has-mmu = <1>; 62*4882a593Smuzhiyun}; 63