1*4882a593SmuzhiyunSTMicroelectronics SoC DWMAC glue layer controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis file documents differences between the core properties in 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/net/stmmac.txt 5*4882a593Smuzhiyunand what is needed on STi platforms to program the stmmac glue logic. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe device node has following properties. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun - compatible : Can be "st,stih415-dwmac", "st,stih416-dwmac", 11*4882a593Smuzhiyun "st,stih407-dwmac", "st,stid127-dwmac". 12*4882a593Smuzhiyun - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which 13*4882a593Smuzhiyun encompases the glue register, and the offset of the control register. 14*4882a593Smuzhiyun - st,gmac_en: this is to enable the gmac into a dedicated sysctl control 15*4882a593Smuzhiyun register available on STiH407 SoC. 16*4882a593Smuzhiyun - pinctrl-0: pin-control for all the MII mode supported. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun - resets : phandle pointing to the system reset controller with correct 20*4882a593Smuzhiyun reset line index for ethernet reset. 21*4882a593Smuzhiyun - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or 22*4882a593Smuzhiyun MAC can generate it. 23*4882a593Smuzhiyun - st,tx-retime-src: This specifies which clk is wired up to the mac for 24*4882a593Smuzhiyun retimeing tx lines. This is totally board dependent and can take one of the 25*4882a593Smuzhiyun posssible values from "txclk", "clk_125" or "clkgen". 26*4882a593Smuzhiyun If not passed, the internal clock will be used by default. 27*4882a593Smuzhiyun - sti-ethclk: this is the phy clock. 28*4882a593Smuzhiyun - sti-clkconf: this is an extra sysconfig register, available in new SoCs, 29*4882a593Smuzhiyun to program the clk retiming. 30*4882a593Smuzhiyun - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g. 31*4882a593Smuzhiyun STiH407. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunethernet0: dwmac@9630000 { 36*4882a593Smuzhiyun device_type = "network"; 37*4882a593Smuzhiyun compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 38*4882a593Smuzhiyun reg = <0x9630000 0x8000>; 39*4882a593Smuzhiyun reg-names = "stmmaceth"; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun st,syscon = <&syscfg_sbc_reg 0x80>; 42*4882a593Smuzhiyun st,gmac_en; 43*4882a593Smuzhiyun resets = <&softreset STIH407_ETH1_SOFTRESET>; 44*4882a593Smuzhiyun reset-names = "stmmaceth"; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>, 47*4882a593Smuzhiyun <GIC_SPI 99 IRQ_TYPE_NONE>, 48*4882a593Smuzhiyun <GIC_SPI 100 IRQ_TYPE_NONE>; 49*4882a593Smuzhiyun interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun snps,pbl = <32>; 52*4882a593Smuzhiyun snps,mixed-burst; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun pinctrl-names = "default"; 55*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_rgmii1>; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun clock-names = "stmmaceth", "sti-ethclk"; 58*4882a593Smuzhiyun clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>, 59*4882a593Smuzhiyun <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>; 60*4882a593Smuzhiyun}; 61