1*4882a593SmuzhiyunAltera SOCFPGA SoC DWMAC controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is a variant of the dwmac/stmmac driver an inherits all descriptions 4*4882a593Smuzhiyunpresent in Documentation/devicetree/bindings/net/stmmac.txt. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe device node has additional properties: 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun - compatible : For Cyclone5/Arria5 SoCs it should contain 10*4882a593Smuzhiyun "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs 11*4882a593Smuzhiyun "altr,socfpga-stmmac-a10-s10". 12*4882a593Smuzhiyun Along with "snps,dwmac" and any applicable more detailed 13*4882a593Smuzhiyun designware version numbers documented in stmmac.txt 14*4882a593Smuzhiyun - altr,sysmgr-syscon : Should be the phandle to the system manager node that 15*4882a593Smuzhiyun encompasses the glue register, the register offset, and the register shift. 16*4882a593Smuzhiyun On Cyclone5/Arria5, the register shift represents the PHY mode bits, while 17*4882a593Smuzhiyun on the Arria10/Stratix10/Agilex platforms, the register shift represents 18*4882a593Smuzhiyun bit for each emac to enable/disable signals from the FPGA fabric to the 19*4882a593Smuzhiyun EMAC modules. 20*4882a593Smuzhiyun - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock 21*4882a593Smuzhiyun for ptp ref clk. This affects all emacs as the clock is common. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunOptional properties: 24*4882a593Smuzhiyunaltr,emac-splitter: Should be the phandle to the emac splitter soft IP node if 25*4882a593Smuzhiyun DWMAC controller is connected emac splitter. 26*4882a593Smuzhiyunphy-mode: The phy mode the ethernet operates in 27*4882a593Smuzhiyunaltr,sgmii-to-sgmii-converter: phandle to the TSE SGMII converter 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunThis device node has additional phandle dependency, the sgmii converter: 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunRequired properties: 32*4882a593Smuzhiyun - compatible : Should be altr,gmii-to-sgmii-2.0 33*4882a593Smuzhiyun - reg-names : Should be "eth_tse_control_port" 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunExample: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyungmii_to_sgmii_converter: phy@100000240 { 38*4882a593Smuzhiyun compatible = "altr,gmii-to-sgmii-2.0"; 39*4882a593Smuzhiyun reg = <0x00000001 0x00000240 0x00000008>, 40*4882a593Smuzhiyun <0x00000001 0x00000200 0x00000040>; 41*4882a593Smuzhiyun reg-names = "eth_tse_control_port"; 42*4882a593Smuzhiyun clocks = <&sgmii_1_clk_0 &emac1 1 &sgmii_clk_125 &sgmii_clk_125>; 43*4882a593Smuzhiyun clock-names = "tse_pcs_ref_clk_clock_connection", "tse_rx_cdr_refclk"; 44*4882a593Smuzhiyun}; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyungmac0: ethernet@ff700000 { 47*4882a593Smuzhiyun compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; 48*4882a593Smuzhiyun altr,sysmgr-syscon = <&sysmgr 0x60 0>; 49*4882a593Smuzhiyun reg = <0xff700000 0x2000>; 50*4882a593Smuzhiyun interrupts = <0 115 4>; 51*4882a593Smuzhiyun interrupt-names = "macirq"; 52*4882a593Smuzhiyun mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ 53*4882a593Smuzhiyun clocks = <&emac_0_clk>; 54*4882a593Smuzhiyun clock-names = "stmmaceth"; 55*4882a593Smuzhiyun phy-mode = "sgmii"; 56*4882a593Smuzhiyun altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>; 57*4882a593Smuzhiyun}; 58