1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/net/snps,dwmac.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Synopsys DesignWare MAC Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Alexandre Torgue <alexandre.torgue@st.com> 11*4882a593Smuzhiyun - Giuseppe Cavallaro <peppe.cavallaro@st.com> 12*4882a593Smuzhiyun - Jose Abreu <joabreu@synopsys.com> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun# Select every compatible, including the deprecated ones. This way, we 15*4882a593Smuzhiyun# will be able to report a warning when we have that compatible, since 16*4882a593Smuzhiyun# we will validate the node thanks to the select, but won't report it 17*4882a593Smuzhiyun# as a valid value in the compatible property description 18*4882a593Smuzhiyunselect: 19*4882a593Smuzhiyun properties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun contains: 22*4882a593Smuzhiyun enum: 23*4882a593Smuzhiyun - snps,dwmac 24*4882a593Smuzhiyun - snps,dwmac-3.50a 25*4882a593Smuzhiyun - snps,dwmac-3.610 26*4882a593Smuzhiyun - snps,dwmac-3.70a 27*4882a593Smuzhiyun - snps,dwmac-3.710 28*4882a593Smuzhiyun - snps,dwmac-4.00 29*4882a593Smuzhiyun - snps,dwmac-4.10a 30*4882a593Smuzhiyun - snps,dwmac-4.20a 31*4882a593Smuzhiyun - snps,dwxgmac 32*4882a593Smuzhiyun - snps,dwxgmac-2.10 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun # Deprecated 35*4882a593Smuzhiyun - st,spear600-gmac 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun required: 38*4882a593Smuzhiyun - compatible 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunproperties: 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun # We need to include all the compatibles from schemas that will 43*4882a593Smuzhiyun # include that schemas, otherwise compatible won't validate for 44*4882a593Smuzhiyun # those. 45*4882a593Smuzhiyun compatible: 46*4882a593Smuzhiyun contains: 47*4882a593Smuzhiyun enum: 48*4882a593Smuzhiyun - allwinner,sun7i-a20-gmac 49*4882a593Smuzhiyun - allwinner,sun8i-a83t-emac 50*4882a593Smuzhiyun - allwinner,sun8i-h3-emac 51*4882a593Smuzhiyun - allwinner,sun8i-r40-emac 52*4882a593Smuzhiyun - allwinner,sun8i-v3s-emac 53*4882a593Smuzhiyun - allwinner,sun50i-a64-emac 54*4882a593Smuzhiyun - amlogic,meson6-dwmac 55*4882a593Smuzhiyun - amlogic,meson8b-dwmac 56*4882a593Smuzhiyun - amlogic,meson8m2-dwmac 57*4882a593Smuzhiyun - amlogic,meson-gxbb-dwmac 58*4882a593Smuzhiyun - amlogic,meson-axg-dwmac 59*4882a593Smuzhiyun - rockchip,px30-gmac 60*4882a593Smuzhiyun - rockchip,rk3128-gmac 61*4882a593Smuzhiyun - rockchip,rk3228-gmac 62*4882a593Smuzhiyun - rockchip,rk3288-gmac 63*4882a593Smuzhiyun - rockchip,rk3328-gmac 64*4882a593Smuzhiyun - rockchip,rk3366-gmac 65*4882a593Smuzhiyun - rockchip,rk3368-gmac 66*4882a593Smuzhiyun - rockchip,rk3399-gmac 67*4882a593Smuzhiyun - rockchip,rv1108-gmac 68*4882a593Smuzhiyun - snps,dwmac 69*4882a593Smuzhiyun - snps,dwmac-3.50a 70*4882a593Smuzhiyun - snps,dwmac-3.610 71*4882a593Smuzhiyun - snps,dwmac-3.70a 72*4882a593Smuzhiyun - snps,dwmac-3.710 73*4882a593Smuzhiyun - snps,dwmac-4.00 74*4882a593Smuzhiyun - snps,dwmac-4.10a 75*4882a593Smuzhiyun - snps,dwmac-4.20a 76*4882a593Smuzhiyun - snps,dwxgmac 77*4882a593Smuzhiyun - snps,dwxgmac-2.10 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun reg: 80*4882a593Smuzhiyun minItems: 1 81*4882a593Smuzhiyun maxItems: 2 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun interrupts: 84*4882a593Smuzhiyun minItems: 1 85*4882a593Smuzhiyun maxItems: 3 86*4882a593Smuzhiyun items: 87*4882a593Smuzhiyun - description: Combined signal for various interrupt events 88*4882a593Smuzhiyun - description: The interrupt to manage the remote wake-up packet detection 89*4882a593Smuzhiyun - description: The interrupt that occurs when Rx exits the LPI state 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun interrupt-names: 92*4882a593Smuzhiyun minItems: 1 93*4882a593Smuzhiyun maxItems: 3 94*4882a593Smuzhiyun items: 95*4882a593Smuzhiyun - const: macirq 96*4882a593Smuzhiyun - const: eth_wake_irq 97*4882a593Smuzhiyun - const: eth_lpi 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun clocks: 100*4882a593Smuzhiyun minItems: 1 101*4882a593Smuzhiyun maxItems: 8 102*4882a593Smuzhiyun additionalItems: true 103*4882a593Smuzhiyun items: 104*4882a593Smuzhiyun - description: GMAC main clock 105*4882a593Smuzhiyun - description: Peripheral registers interface clock 106*4882a593Smuzhiyun - description: 107*4882a593Smuzhiyun PTP reference clock. This clock is used for programming the 108*4882a593Smuzhiyun Timestamp Addend Register. If not passed then the system 109*4882a593Smuzhiyun clock will be used and this is fine on some platforms. 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun clock-names: 112*4882a593Smuzhiyun minItems: 1 113*4882a593Smuzhiyun maxItems: 8 114*4882a593Smuzhiyun additionalItems: true 115*4882a593Smuzhiyun contains: 116*4882a593Smuzhiyun enum: 117*4882a593Smuzhiyun - stmmaceth 118*4882a593Smuzhiyun - pclk 119*4882a593Smuzhiyun - ptp_ref 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun resets: 122*4882a593Smuzhiyun maxItems: 1 123*4882a593Smuzhiyun description: 124*4882a593Smuzhiyun MAC Reset signal. 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun reset-names: 127*4882a593Smuzhiyun const: stmmaceth 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun mac-mode: 130*4882a593Smuzhiyun $ref: ethernet-controller.yaml#/properties/phy-connection-type 131*4882a593Smuzhiyun description: 132*4882a593Smuzhiyun The property is identical to 'phy-mode', and assumes that there is mode 133*4882a593Smuzhiyun converter in-between the MAC & PHY (e.g. GMII-to-RGMII). This converter 134*4882a593Smuzhiyun can be passive (no SW requirement), and requires that the MAC operate 135*4882a593Smuzhiyun in a different mode than the PHY in order to function. 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun snps,axi-config: 138*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/phandle 139*4882a593Smuzhiyun description: 140*4882a593Smuzhiyun AXI BUS Mode parameters. Phandle to a node that can contain the 141*4882a593Smuzhiyun following properties 142*4882a593Smuzhiyun * snps,lpi_en, enable Low Power Interface 143*4882a593Smuzhiyun * snps,xit_frm, unlock on WoL 144*4882a593Smuzhiyun * snps,wr_osr_lmt, max write outstanding req. limit 145*4882a593Smuzhiyun * snps,rd_osr_lmt, max read outstanding req. limit 146*4882a593Smuzhiyun * snps,kbbe, do not cross 1KiB boundary. 147*4882a593Smuzhiyun * snps,blen, this is a vector of supported burst length. 148*4882a593Smuzhiyun * snps,fb, fixed-burst 149*4882a593Smuzhiyun * snps,mb, mixed-burst 150*4882a593Smuzhiyun * snps,rb, rebuild INCRx Burst 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun snps,mtl-rx-config: 153*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/phandle 154*4882a593Smuzhiyun description: 155*4882a593Smuzhiyun Multiple RX Queues parameters. Phandle to a node that can 156*4882a593Smuzhiyun contain the following properties 157*4882a593Smuzhiyun * snps,rx-queues-to-use, number of RX queues to be used in the 158*4882a593Smuzhiyun driver 159*4882a593Smuzhiyun * Choose one of these RX scheduling algorithms 160*4882a593Smuzhiyun * snps,rx-sched-sp, Strict priority 161*4882a593Smuzhiyun * snps,rx-sched-wsp, Weighted Strict priority 162*4882a593Smuzhiyun * For each RX queue 163*4882a593Smuzhiyun * Choose one of these modes 164*4882a593Smuzhiyun * snps,dcb-algorithm, Queue to be enabled as DCB 165*4882a593Smuzhiyun * snps,avb-algorithm, Queue to be enabled as AVB 166*4882a593Smuzhiyun * snps,map-to-dma-channel, Channel to map 167*4882a593Smuzhiyun * Specifiy specific packet routing 168*4882a593Smuzhiyun * snps,route-avcp, AV Untagged Control packets 169*4882a593Smuzhiyun * snps,route-ptp, PTP Packets 170*4882a593Smuzhiyun * snps,route-dcbcp, DCB Control Packets 171*4882a593Smuzhiyun * snps,route-up, Untagged Packets 172*4882a593Smuzhiyun * snps,route-multi-broad, Multicast & Broadcast Packets 173*4882a593Smuzhiyun * snps,priority, RX queue priority (Range 0x0 to 0xF) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun snps,mtl-tx-config: 176*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/phandle 177*4882a593Smuzhiyun description: 178*4882a593Smuzhiyun Multiple TX Queues parameters. Phandle to a node that can 179*4882a593Smuzhiyun contain the following properties 180*4882a593Smuzhiyun * snps,tx-queues-to-use, number of TX queues to be used in the 181*4882a593Smuzhiyun driver 182*4882a593Smuzhiyun * Choose one of these TX scheduling algorithms 183*4882a593Smuzhiyun * snps,tx-sched-wrr, Weighted Round Robin 184*4882a593Smuzhiyun * snps,tx-sched-wfq, Weighted Fair Queuing 185*4882a593Smuzhiyun * snps,tx-sched-dwrr, Deficit Weighted Round Robin 186*4882a593Smuzhiyun * snps,tx-sched-sp, Strict priority 187*4882a593Smuzhiyun * For each TX queue 188*4882a593Smuzhiyun * snps,weight, TX queue weight (if using a DCB weight 189*4882a593Smuzhiyun algorithm) 190*4882a593Smuzhiyun * Choose one of these modes 191*4882a593Smuzhiyun * snps,dcb-algorithm, TX queue will be working in DCB 192*4882a593Smuzhiyun * snps,avb-algorithm, TX queue will be working in AVB 193*4882a593Smuzhiyun [Attention] Queue 0 is reserved for legacy traffic 194*4882a593Smuzhiyun and so no AVB is available in this queue. 195*4882a593Smuzhiyun * Configure Credit Base Shaper (if AVB Mode selected) 196*4882a593Smuzhiyun * snps,send_slope, enable Low Power Interface 197*4882a593Smuzhiyun * snps,idle_slope, unlock on WoL 198*4882a593Smuzhiyun * snps,high_credit, max write outstanding req. limit 199*4882a593Smuzhiyun * snps,low_credit, max read outstanding req. limit 200*4882a593Smuzhiyun * snps,priority, TX queue priority (Range 0x0 to 0xF) 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun snps,reset-gpio: 203*4882a593Smuzhiyun deprecated: true 204*4882a593Smuzhiyun maxItems: 1 205*4882a593Smuzhiyun description: 206*4882a593Smuzhiyun PHY Reset GPIO 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun snps,reset-active-low: 209*4882a593Smuzhiyun deprecated: true 210*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 211*4882a593Smuzhiyun description: 212*4882a593Smuzhiyun Indicates that the PHY Reset is active low 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun snps,reset-delays-us: 215*4882a593Smuzhiyun deprecated: true 216*4882a593Smuzhiyun description: 217*4882a593Smuzhiyun Triplet of delays. The 1st cell is reset pre-delay in micro 218*4882a593Smuzhiyun seconds. The 2nd cell is reset pulse in micro seconds. The 3rd 219*4882a593Smuzhiyun cell is reset post-delay in micro seconds. 220*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32-array 221*4882a593Smuzhiyun minItems: 3 222*4882a593Smuzhiyun maxItems: 3 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun snps,aal: 225*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 226*4882a593Smuzhiyun description: 227*4882a593Smuzhiyun Use Address-Aligned Beats 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun snps,fixed-burst: 230*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 231*4882a593Smuzhiyun description: 232*4882a593Smuzhiyun Program the DMA to use the fixed burst mode 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun snps,mixed-burst: 235*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 236*4882a593Smuzhiyun description: 237*4882a593Smuzhiyun Program the DMA to use the mixed burst mode 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun snps,force_thresh_dma_mode: 240*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 241*4882a593Smuzhiyun description: 242*4882a593Smuzhiyun Force DMA to use the threshold mode for both tx and rx 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun snps,force_sf_dma_mode: 245*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 246*4882a593Smuzhiyun description: 247*4882a593Smuzhiyun Force DMA to use the Store and Forward mode for both tx and 248*4882a593Smuzhiyun rx. This flag is ignored if force_thresh_dma_mode is set. 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun snps,en-tx-lpi-clockgating: 251*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 252*4882a593Smuzhiyun description: 253*4882a593Smuzhiyun Enable gating of the MAC TX clock during TX low-power mode 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun snps,multicast-filter-bins: 256*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 257*4882a593Smuzhiyun description: 258*4882a593Smuzhiyun Number of multicast filter hash bins supported by this device 259*4882a593Smuzhiyun instance 260*4882a593Smuzhiyun 261*4882a593Smuzhiyun snps,perfect-filter-entries: 262*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 263*4882a593Smuzhiyun description: 264*4882a593Smuzhiyun Number of perfect filter entries supported by this device 265*4882a593Smuzhiyun instance 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun snps,ps-speed: 268*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 269*4882a593Smuzhiyun description: 270*4882a593Smuzhiyun Port selection speed that can be passed to the core when PCS 271*4882a593Smuzhiyun is supported. For example, this is used in case of SGMII and 272*4882a593Smuzhiyun MAC2MAC connection. 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun snps,flow-ctrl: 275*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 276*4882a593Smuzhiyun description: 277*4882a593Smuzhiyun Disable or enable flow control for controller. 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun mdio: 280*4882a593Smuzhiyun type: object 281*4882a593Smuzhiyun description: 282*4882a593Smuzhiyun Creates and registers an MDIO bus. 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun properties: 285*4882a593Smuzhiyun compatible: 286*4882a593Smuzhiyun const: snps,dwmac-mdio 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun required: 289*4882a593Smuzhiyun - compatible 290*4882a593Smuzhiyun 291*4882a593Smuzhiyunrequired: 292*4882a593Smuzhiyun - compatible 293*4882a593Smuzhiyun - reg 294*4882a593Smuzhiyun - interrupts 295*4882a593Smuzhiyun - interrupt-names 296*4882a593Smuzhiyun - phy-mode 297*4882a593Smuzhiyun 298*4882a593Smuzhiyundependencies: 299*4882a593Smuzhiyun snps,reset-active-low: ["snps,reset-gpio"] 300*4882a593Smuzhiyun snps,reset-delay-us: ["snps,reset-gpio"] 301*4882a593Smuzhiyun 302*4882a593SmuzhiyunallOf: 303*4882a593Smuzhiyun - $ref: "ethernet-controller.yaml#" 304*4882a593Smuzhiyun - if: 305*4882a593Smuzhiyun properties: 306*4882a593Smuzhiyun compatible: 307*4882a593Smuzhiyun contains: 308*4882a593Smuzhiyun enum: 309*4882a593Smuzhiyun - allwinner,sun7i-a20-gmac 310*4882a593Smuzhiyun - allwinner,sun8i-a83t-emac 311*4882a593Smuzhiyun - allwinner,sun8i-h3-emac 312*4882a593Smuzhiyun - allwinner,sun8i-r40-emac 313*4882a593Smuzhiyun - allwinner,sun8i-v3s-emac 314*4882a593Smuzhiyun - allwinner,sun50i-a64-emac 315*4882a593Smuzhiyun - snps,dwxgmac 316*4882a593Smuzhiyun - snps,dwxgmac-2.10 317*4882a593Smuzhiyun - st,spear600-gmac 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun then: 320*4882a593Smuzhiyun properties: 321*4882a593Smuzhiyun snps,pbl: 322*4882a593Smuzhiyun description: 323*4882a593Smuzhiyun Programmable Burst Length (tx and rx) 324*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 325*4882a593Smuzhiyun enum: [2, 4, 8] 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun snps,txpbl: 328*4882a593Smuzhiyun description: 329*4882a593Smuzhiyun Tx Programmable Burst Length. If set, DMA tx will use this 330*4882a593Smuzhiyun value rather than snps,pbl. 331*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 332*4882a593Smuzhiyun enum: [2, 4, 8] 333*4882a593Smuzhiyun 334*4882a593Smuzhiyun snps,rxpbl: 335*4882a593Smuzhiyun description: 336*4882a593Smuzhiyun Rx Programmable Burst Length. If set, DMA rx will use this 337*4882a593Smuzhiyun value rather than snps,pbl. 338*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/uint32 339*4882a593Smuzhiyun enum: [2, 4, 8] 340*4882a593Smuzhiyun 341*4882a593Smuzhiyun snps,no-pbl-x8: 342*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 343*4882a593Smuzhiyun description: 344*4882a593Smuzhiyun Don\'t multiply the pbl/txpbl/rxpbl values by 8. For core 345*4882a593Smuzhiyun rev < 3.50, don\'t multiply the values by 4. 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun - if: 348*4882a593Smuzhiyun properties: 349*4882a593Smuzhiyun compatible: 350*4882a593Smuzhiyun contains: 351*4882a593Smuzhiyun enum: 352*4882a593Smuzhiyun - allwinner,sun7i-a20-gmac 353*4882a593Smuzhiyun - allwinner,sun8i-a83t-emac 354*4882a593Smuzhiyun - allwinner,sun8i-h3-emac 355*4882a593Smuzhiyun - allwinner,sun8i-r40-emac 356*4882a593Smuzhiyun - allwinner,sun8i-v3s-emac 357*4882a593Smuzhiyun - allwinner,sun50i-a64-emac 358*4882a593Smuzhiyun - snps,dwmac-4.00 359*4882a593Smuzhiyun - snps,dwmac-4.10a 360*4882a593Smuzhiyun - snps,dwmac-4.20a 361*4882a593Smuzhiyun - snps,dwxgmac 362*4882a593Smuzhiyun - snps,dwxgmac-2.10 363*4882a593Smuzhiyun - st,spear600-gmac 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun then: 366*4882a593Smuzhiyun properties: 367*4882a593Smuzhiyun snps,tso: 368*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/flag 369*4882a593Smuzhiyun description: 370*4882a593Smuzhiyun Enables the TSO feature otherwise it will be managed by 371*4882a593Smuzhiyun MAC HW capability register. 372*4882a593Smuzhiyun 373*4882a593SmuzhiyunadditionalProperties: true 374*4882a593Smuzhiyun 375*4882a593Smuzhiyunexamples: 376*4882a593Smuzhiyun - | 377*4882a593Smuzhiyun stmmac_axi_setup: stmmac-axi-config { 378*4882a593Smuzhiyun snps,wr_osr_lmt = <0xf>; 379*4882a593Smuzhiyun snps,rd_osr_lmt = <0xf>; 380*4882a593Smuzhiyun snps,blen = <256 128 64 32 0 0 0>; 381*4882a593Smuzhiyun }; 382*4882a593Smuzhiyun 383*4882a593Smuzhiyun mtl_rx_setup: rx-queues-config { 384*4882a593Smuzhiyun snps,rx-queues-to-use = <1>; 385*4882a593Smuzhiyun snps,rx-sched-sp; 386*4882a593Smuzhiyun queue0 { 387*4882a593Smuzhiyun snps,dcb-algorithm; 388*4882a593Smuzhiyun snps,map-to-dma-channel = <0x0>; 389*4882a593Smuzhiyun snps,priority = <0x0>; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun mtl_tx_setup: tx-queues-config { 394*4882a593Smuzhiyun snps,tx-queues-to-use = <2>; 395*4882a593Smuzhiyun snps,tx-sched-wrr; 396*4882a593Smuzhiyun queue0 { 397*4882a593Smuzhiyun snps,weight = <0x10>; 398*4882a593Smuzhiyun snps,dcb-algorithm; 399*4882a593Smuzhiyun snps,priority = <0x0>; 400*4882a593Smuzhiyun }; 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun queue1 { 403*4882a593Smuzhiyun snps,avb-algorithm; 404*4882a593Smuzhiyun snps,send_slope = <0x1000>; 405*4882a593Smuzhiyun snps,idle_slope = <0x1000>; 406*4882a593Smuzhiyun snps,high_credit = <0x3E800>; 407*4882a593Smuzhiyun snps,low_credit = <0xFFC18000>; 408*4882a593Smuzhiyun snps,priority = <0x1>; 409*4882a593Smuzhiyun }; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun gmac0: ethernet@e0800000 { 413*4882a593Smuzhiyun compatible = "snps,dwxgmac-2.10", "snps,dwxgmac"; 414*4882a593Smuzhiyun reg = <0xe0800000 0x8000>; 415*4882a593Smuzhiyun interrupt-parent = <&vic1>; 416*4882a593Smuzhiyun interrupts = <24 23 22>; 417*4882a593Smuzhiyun interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 418*4882a593Smuzhiyun mac-address = [000000000000]; /* Filled in by U-Boot */ 419*4882a593Smuzhiyun max-frame-size = <3800>; 420*4882a593Smuzhiyun phy-mode = "gmii"; 421*4882a593Smuzhiyun snps,multicast-filter-bins = <256>; 422*4882a593Smuzhiyun snps,perfect-filter-entries = <128>; 423*4882a593Smuzhiyun rx-fifo-depth = <16384>; 424*4882a593Smuzhiyun tx-fifo-depth = <16384>; 425*4882a593Smuzhiyun clocks = <&clock>; 426*4882a593Smuzhiyun clock-names = "stmmaceth"; 427*4882a593Smuzhiyun snps,axi-config = <&stmmac_axi_setup>; 428*4882a593Smuzhiyun snps,mtl-rx-config = <&mtl_rx_setup>; 429*4882a593Smuzhiyun snps,mtl-tx-config = <&mtl_tx_setup>; 430*4882a593Smuzhiyun mdio0 { 431*4882a593Smuzhiyun #address-cells = <1>; 432*4882a593Smuzhiyun #size-cells = <0>; 433*4882a593Smuzhiyun compatible = "snps,dwmac-mdio"; 434*4882a593Smuzhiyun phy1: ethernet-phy@0 { 435*4882a593Smuzhiyun reg = <0>; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun }; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun# FIXME: We should set it, but it would report all the generic 441*4882a593Smuzhiyun# properties as additional properties. 442*4882a593Smuzhiyun# additionalProperties: false 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun... 445