1*4882a593SmuzhiyunRalink Frame Engine Ethernet controller 2*4882a593Smuzhiyun======================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Ralink frame engine ethernet controller can be found on Ralink and 5*4882a593SmuzhiyunMediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8). 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunDepending on the SoC, there is a number of ports connected to the CPU port 8*4882a593Smuzhiyundirectly and/or via a (gigabit-)switch. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun* Ethernet controller node 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunRequired properties: 13*4882a593Smuzhiyun- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth", 14*4882a593Smuzhiyun "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth", 15*4882a593Smuzhiyun "mediatek,mt7620-eth", "mediatek,mt7621-eth" 16*4882a593Smuzhiyun- reg: Address and length of the register set for the device 17*4882a593Smuzhiyun- interrupts: Should contain the frame engines interrupt 18*4882a593Smuzhiyun- resets: Should contain the frame engines resets 19*4882a593Smuzhiyun- reset-names: Should contain the reset names "fe". If a switch is present 20*4882a593Smuzhiyun "esw" is also required. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun* Ethernet port node 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunRequired properties: 26*4882a593Smuzhiyun- compatible: Should be "ralink,eth-port" 27*4882a593Smuzhiyun- reg: The number of the physical port 28*4882a593Smuzhiyun- phy-handle: reference to the node describing the phy 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyunmdio-bus { 33*4882a593Smuzhiyun ... 34*4882a593Smuzhiyun phy0: ethernet-phy@0 { 35*4882a593Smuzhiyun phy-mode = "mii"; 36*4882a593Smuzhiyun reg = <0>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun}; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyunethernet@400000 { 41*4882a593Smuzhiyun compatible = "ralink,rt2880-eth"; 42*4882a593Smuzhiyun reg = <0x00400000 10000>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <0>; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun resets = <&rstctrl 18>; 48*4882a593Smuzhiyun reset-names = "fe"; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun interrupt-parent = <&cpuintc>; 51*4882a593Smuzhiyun interrupts = <5>; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun port@0 { 54*4882a593Smuzhiyun compatible = "ralink,eth-port"; 55*4882a593Smuzhiyun reg = <0>; 56*4882a593Smuzhiyun phy-handle = <&phy0>; 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun}; 60