1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0+ 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/net/qca,ar803x.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Atheros AR803x PHY 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Andrew Lunn <andrew@lunn.ch> 11*4882a593Smuzhiyun - Florian Fainelli <f.fainelli@gmail.com> 12*4882a593Smuzhiyun - Heiner Kallweit <hkallweit1@gmail.com> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyundescription: | 15*4882a593Smuzhiyun Bindings for Qualcomm Atheros AR803x PHYs 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunallOf: 18*4882a593Smuzhiyun - $ref: ethernet-phy.yaml# 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun qca,clk-out-frequency: 22*4882a593Smuzhiyun description: Clock output frequency in Hertz. 23*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 24*4882a593Smuzhiyun enum: [25000000, 50000000, 62500000, 125000000] 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun qca,clk-out-strength: 27*4882a593Smuzhiyun description: Clock output driver strength. 28*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32 29*4882a593Smuzhiyun enum: [0, 1, 2] 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun qca,keep-pll-enabled: 32*4882a593Smuzhiyun description: | 33*4882a593Smuzhiyun If set, keep the PLL enabled even if there is no link. Useful if you 34*4882a593Smuzhiyun want to use the clock output without an ethernet link. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun Only supported on the AR8031. 37*4882a593Smuzhiyun type: boolean 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun vddio-supply: 40*4882a593Smuzhiyun description: | 41*4882a593Smuzhiyun RGMII I/O voltage regulator (see regulator/regulator.yaml). 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can 44*4882a593Smuzhiyun either connect this to the vddio-regulator (1.5V / 1.8V) or the 45*4882a593Smuzhiyun vddh-regulator (2.5V). 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun Only supported on the AR8031. 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun vddio-regulator: 50*4882a593Smuzhiyun type: object 51*4882a593Smuzhiyun description: 52*4882a593Smuzhiyun Initial data for the VDDIO regulator. Set this to 1.5V or 1.8V. 53*4882a593Smuzhiyun $ref: /schemas/regulator/regulator.yaml 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun vddh-regulator: 56*4882a593Smuzhiyun type: object 57*4882a593Smuzhiyun description: 58*4882a593Smuzhiyun Dummy subnode to model the external connection of the PHY VDDH 59*4882a593Smuzhiyun regulator to VDDIO. 60*4882a593Smuzhiyun $ref: /schemas/regulator/regulator.yaml 61*4882a593Smuzhiyun 62*4882a593SmuzhiyununevaluatedProperties: false 63*4882a593Smuzhiyun 64*4882a593Smuzhiyunexamples: 65*4882a593Smuzhiyun - | 66*4882a593Smuzhiyun #include <dt-bindings/net/qca-ar803x.h> 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun ethernet { 69*4882a593Smuzhiyun #address-cells = <1>; 70*4882a593Smuzhiyun #size-cells = <0>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun phy-mode = "rgmii-id"; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun ethernet-phy@0 { 75*4882a593Smuzhiyun reg = <0>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun qca,clk-out-frequency = <125000000>; 78*4882a593Smuzhiyun qca,clk-out-strength = <AR803X_STRENGTH_FULL>; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun vddio-supply = <&vddio>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun vddio: vddio-regulator { 83*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 84*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun - | 89*4882a593Smuzhiyun #include <dt-bindings/net/qca-ar803x.h> 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun ethernet { 92*4882a593Smuzhiyun #address-cells = <1>; 93*4882a593Smuzhiyun #size-cells = <0>; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun phy-mode = "rgmii-id"; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun ethernet-phy@0 { 98*4882a593Smuzhiyun reg = <0>; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun qca,clk-out-frequency = <50000000>; 101*4882a593Smuzhiyun qca,keep-pll-enabled; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun vddio-supply = <&vddh>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun vddh: vddh-regulator { 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109