1*4882a593Smuzhiyun* Oxford Semiconductor OXNAS DWMAC Ethernet controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe device inherits all the properties of the dwmac/stmmac devices 4*4882a593Smuzhiyundescribed in the file stmmac.txt in the current directory with the 5*4882a593Smuzhiyunfollowing changes. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties on all platforms: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: For the OX820 SoC, it should be : 10*4882a593Smuzhiyun - "oxsemi,ox820-dwmac" to select glue 11*4882a593Smuzhiyun - "snps,dwmac-3.512" to select IP version. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun- clocks: Should contain phandles to the following clocks 14*4882a593Smuzhiyun- clock-names: Should contain the following: 15*4882a593Smuzhiyun - "stmmaceth" for the host clock - see stmmac.txt 16*4882a593Smuzhiyun - "gmac" for the peripheral gate clock 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- oxsemi,sys-ctrl: a phandle to the system controller syscon node 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample : 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunetha: ethernet@40400000 { 23*4882a593Smuzhiyun compatible = "oxsemi,ox820-dwmac", "snps,dwmac-3.512"; 24*4882a593Smuzhiyun reg = <0x40400000 0x2000>; 25*4882a593Smuzhiyun interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 26*4882a593Smuzhiyun <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 27*4882a593Smuzhiyun interrupt-names = "macirq", "eth_wake_irq"; 28*4882a593Smuzhiyun mac-address = [000000000000]; /* Filled in by U-Boot */ 29*4882a593Smuzhiyun phy-mode = "rgmii"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>; 32*4882a593Smuzhiyun clock-names = "gmac", "stmmaceth"; 33*4882a593Smuzhiyun resets = <&reset RESET_MAC>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Regmap for sys registers */ 36*4882a593Smuzhiyun oxsemi,sys-ctrl = <&sys>; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun}; 39