1*4882a593Smuzhiyun* Marvell International Ltd. NCI NFC Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should be: 5*4882a593Smuzhiyun - "marvell,nfc-uart" or "mrvl,nfc-uart" for UART devices 6*4882a593Smuzhiyun - "marvell,nfc-i2c" for I2C devices 7*4882a593Smuzhiyun - "marvell,nfc-spi" for SPI devices 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunOptional SoC specific properties: 10*4882a593Smuzhiyun- pinctrl-names: Contains only one value - "default". 11*4882a593Smuzhiyun- pintctrl-0: Specifies the pin control groups used for this controller. 12*4882a593Smuzhiyun- reset-n-io: Output GPIO pin used to reset the chip (active low). 13*4882a593Smuzhiyun- hci-muxed: Specifies that the chip is muxing NCI over HCI frames. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional UART-based chip specific properties: 16*4882a593Smuzhiyun- flow-control: Specifies that the chip is using RTS/CTS. 17*4882a593Smuzhiyun- break-control: Specifies that the chip needs specific break management. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional I2C-based chip specific properties: 20*4882a593Smuzhiyun- i2c-int-falling: Specifies that the chip read event shall be trigged on 21*4882a593Smuzhiyun falling edge. 22*4882a593Smuzhiyun- i2c-int-rising: Specifies that the chip read event shall be trigged on 23*4882a593Smuzhiyun rising edge. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample (for ARM-based BeagleBoard Black with 88W8887 on UART5): 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun&uart5 { 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun nfcmrvluart: nfcmrvluart@5 { 30*4882a593Smuzhiyun compatible = "marvell,nfc-uart"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun reset-n-io = <&gpio3 16 0>; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun hci-muxed; 35*4882a593Smuzhiyun flow-control; 36*4882a593Smuzhiyun } 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunExample (for ARM-based BeagleBoard Black with 88W8887 on I2C1): 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun&i2c1 { 43*4882a593Smuzhiyun clock-frequency = <400000>; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun nfcmrvli2c0: i2c@1 { 46*4882a593Smuzhiyun compatible = "marvell,nfc-i2c"; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun reg = <0x8>; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* I2C INT configuration */ 51*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 52*4882a593Smuzhiyun interrupts = <21 0>; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* I2C INT trigger configuration */ 55*4882a593Smuzhiyun i2c-int-rising; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Reset IO */ 58*4882a593Smuzhiyun reset-n-io = <&gpio3 19 0>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun}; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunExample (for ARM-based BeagleBoard Black on SPI0): 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun&spi0 { 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun mrvlnfcspi0: spi@0 { 68*4882a593Smuzhiyun compatible = "marvell,nfc-spi"; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun reg = <0>; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* SPI Bus configuration */ 73*4882a593Smuzhiyun spi-max-frequency = <3000000>; 74*4882a593Smuzhiyun spi-cpha; 75*4882a593Smuzhiyun spi-cpol; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* SPI INT configuration */ 78*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 79*4882a593Smuzhiyun interrupts = <17 0>; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* Reset IO */ 82*4882a593Smuzhiyun reset-n-io = <&gpio3 19 0>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun}; 85