1*4882a593SmuzhiyunMicrosemi MII Management Controller (MIIM) / MDIO 2*4882a593Smuzhiyun================================================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunProperties: 5*4882a593Smuzhiyun- compatible: must be "mscc,ocelot-miim" 6*4882a593Smuzhiyun- reg: The base address of the MDIO bus controller register bank. Optionally, a 7*4882a593Smuzhiyun second register bank can be defined if there is an associated reset register 8*4882a593Smuzhiyun for internal PHYs 9*4882a593Smuzhiyun- #address-cells: Must be <1>. 10*4882a593Smuzhiyun- #size-cells: Must be <0>. MDIO addresses have no size component. 11*4882a593Smuzhiyun- interrupts: interrupt specifier (refer to the interrupt binding) 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunTypically an MDIO bus might have several children. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunExample: 16*4882a593Smuzhiyun mdio@107009c { 17*4882a593Smuzhiyun #address-cells = <1>; 18*4882a593Smuzhiyun #size-cells = <0>; 19*4882a593Smuzhiyun compatible = "mscc,ocelot-miim"; 20*4882a593Smuzhiyun reg = <0x107009c 0x36>, <0x10700f0 0x8>; 21*4882a593Smuzhiyun interrupts = <14>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun phy0: ethernet-phy@0 { 24*4882a593Smuzhiyun reg = <0>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27