1*4882a593Smuzhiyun* Microchip ENC28J60 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is a standalone 10 MBit ethernet controller with SPI interface. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunFor each device connected to a SPI bus, define a child node within 6*4882a593Smuzhiyunthe SPI master node. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: Should be "microchip,enc28j60" 10*4882a593Smuzhiyun- reg: Specify the SPI chip select the ENC28J60 is wired to 11*4882a593Smuzhiyun- interrupts: Specify the interrupt index within the interrupt controller (referred 12*4882a593Smuzhiyun to above in interrupt-parent) and interrupt type. The ENC28J60 natively 13*4882a593Smuzhiyun generates falling edge interrupts, however, additional board logic 14*4882a593Smuzhiyun might invert the signal. 15*4882a593Smuzhiyun- pinctrl-names: List of assigned state names, see pinctrl binding documentation. 16*4882a593Smuzhiyun- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line, 17*4882a593Smuzhiyun see also generic and your platform specific pinctrl binding 18*4882a593Smuzhiyun documentation. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunOptional properties: 21*4882a593Smuzhiyun- spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60. 22*4882a593Smuzhiyun According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however, 23*4882a593Smuzhiyun board designs may need to limit this value. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunThe MAC address will be determined using the optional properties 26*4882a593Smuzhiyundefined in ethernet.txt. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample (for NXP i.MX28 with pin control stuff for GPIO irq): 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun ssp2: ssp@80014000 { 31*4882a593Smuzhiyun compatible = "fsl,imx28-spi"; 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enc28j60: ethernet@0 { 36*4882a593Smuzhiyun compatible = "microchip,enc28j60"; 37*4882a593Smuzhiyun pinctrl-names = "default"; 38*4882a593Smuzhiyun pinctrl-0 = <&enc28j60_pins>; 39*4882a593Smuzhiyun reg = <0>; 40*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 41*4882a593Smuzhiyun interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 42*4882a593Smuzhiyun spi-max-frequency = <12000000>; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun pinctrl@80018000 { 47*4882a593Smuzhiyun enc28j60_pins: enc28j60_pins@0 { 48*4882a593Smuzhiyun reg = <0>; 49*4882a593Smuzhiyun fsl,pinmux-ids = < 50*4882a593Smuzhiyun MX28_PAD_AUART0_RTS__GPIO_3_3 /* Interrupt */ 51*4882a593Smuzhiyun >; 52*4882a593Smuzhiyun fsl,drive-strength = <MXS_DRIVE_4mA>; 53*4882a593Smuzhiyun fsl,voltage = <MXS_VOLTAGE_HIGH>; 54*4882a593Smuzhiyun fsl,pull-up = <MXS_PULL_DISABLE>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun }; 57