1*4882a593SmuzhiyunMicrel PHY properties. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThese properties cover the base properties Micrel PHYs. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunOptional properties: 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun - micrel,led-mode : LED mode value to set for PHYs with configurable LEDs. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun Configure the LED mode with single value. The list of PHYs and the 10*4882a593Smuzhiyun bits that are currently supported: 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun KSZ8001: register 0x1e, bits 15..14 13*4882a593Smuzhiyun KSZ8041: register 0x1e, bits 15..14 14*4882a593Smuzhiyun KSZ8021: register 0x1f, bits 5..4 15*4882a593Smuzhiyun KSZ8031: register 0x1f, bits 5..4 16*4882a593Smuzhiyun KSZ8051: register 0x1f, bits 5..4 17*4882a593Smuzhiyun KSZ8081: register 0x1f, bits 5..4 18*4882a593Smuzhiyun KSZ8091: register 0x1f, bits 5..4 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun See the respective PHY datasheet for the mode values. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select 23*4882a593Smuzhiyun bit selects 25 MHz mode 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun Setting the RMII Reference Clock Select bit enables 25 MHz rather 26*4882a593Smuzhiyun than 50 MHz clock mode. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun Note that this option in only needed for certain PHY revisions with a 29*4882a593Smuzhiyun non-standard, inverted function of this configuration bit. 30*4882a593Smuzhiyun Specifically, a clock reference ("rmii-ref" below) is always needed to 31*4882a593Smuzhiyun actually select a mode. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun - clocks, clock-names: contains clocks according to the common clock bindings. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun supported clocks: 36*4882a593Smuzhiyun - KSZ8021, KSZ8031, KSZ8081, KSZ8091: "rmii-ref": The RMII reference 37*4882a593Smuzhiyun input clock. Used to determine the XI input clock. 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun - micrel,fiber-mode: If present the PHY is configured to operate in fiber mode 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun Some PHYs, such as the KSZ8041FTL variant, support fiber mode, enabled 42*4882a593Smuzhiyun by the FXEN boot strapping pin. It can't be determined from the PHY 43*4882a593Smuzhiyun registers whether the PHY is in fiber mode, so this boolean device tree 44*4882a593Smuzhiyun property can be used to describe it. 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun In fiber mode, auto-negotiation is disabled and the PHY can only work in 47*4882a593Smuzhiyun 100base-fx (full and half duplex) modes. 48