1*4882a593SmuzhiyunMicrel KSZ9021/KSZ9031/KSZ9131 Gigabit Ethernet PHY 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunSome boards require special tuning values, particularly when it comes 4*4882a593Smuzhiyunto clock delays. You can specify clock delay values in the PHY OF 5*4882a593Smuzhiyundevice node. Deprecated, but still supported, these properties can 6*4882a593Smuzhiyunalso be added to an Ethernet OF device node. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunNote that these settings are applied after any phy-specific fixup from 9*4882a593Smuzhiyunphy_fixup_list (see phy_init_hw() from drivers/net/phy/phy_device.c), 10*4882a593Smuzhiyunand therefore may overwrite them. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunKSZ9021: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun All skew control options are specified in picoseconds. The minimum 15*4882a593Smuzhiyun value is 0, the maximum value is 3000, and it can be specified in 200ps 16*4882a593Smuzhiyun steps, *but* these values are in not fact what you get because this chip's 17*4882a593Smuzhiyun skew values actually increase in 120ps steps, starting from -840ps. The 18*4882a593Smuzhiyun incorrect values came from an error in the original KSZ9021 datasheet 19*4882a593Smuzhiyun before it was corrected in revision 1.2 (Feb 2014), but it is too late to 20*4882a593Smuzhiyun change the driver now because of the many existing device trees that have 21*4882a593Smuzhiyun been created using values that go up in increments of 200. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun The following table shows the actual skew delay you will get for each of the 24*4882a593Smuzhiyun possible devicetree values, and the number that will be programmed into the 25*4882a593Smuzhiyun corresponding pad skew register: 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun Device Tree Value Delay Pad Skew Register Value 28*4882a593Smuzhiyun ----------------------------------------------------- 29*4882a593Smuzhiyun 0 -840ps 0000 30*4882a593Smuzhiyun 200 -720ps 0001 31*4882a593Smuzhiyun 400 -600ps 0010 32*4882a593Smuzhiyun 600 -480ps 0011 33*4882a593Smuzhiyun 800 -360ps 0100 34*4882a593Smuzhiyun 1000 -240ps 0101 35*4882a593Smuzhiyun 1200 -120ps 0110 36*4882a593Smuzhiyun 1400 0ps 0111 37*4882a593Smuzhiyun 1600 120ps 1000 38*4882a593Smuzhiyun 1800 240ps 1001 39*4882a593Smuzhiyun 2000 360ps 1010 40*4882a593Smuzhiyun 2200 480ps 1011 41*4882a593Smuzhiyun 2400 600ps 1100 42*4882a593Smuzhiyun 2600 720ps 1101 43*4882a593Smuzhiyun 2800 840ps 1110 44*4882a593Smuzhiyun 3000 960ps 1111 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun Optional properties: 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun - rxc-skew-ps : Skew control of RXC pad 49*4882a593Smuzhiyun - rxdv-skew-ps : Skew control of RX CTL pad 50*4882a593Smuzhiyun - txc-skew-ps : Skew control of TXC pad 51*4882a593Smuzhiyun - txen-skew-ps : Skew control of TX CTL pad 52*4882a593Smuzhiyun - rxd0-skew-ps : Skew control of RX data 0 pad 53*4882a593Smuzhiyun - rxd1-skew-ps : Skew control of RX data 1 pad 54*4882a593Smuzhiyun - rxd2-skew-ps : Skew control of RX data 2 pad 55*4882a593Smuzhiyun - rxd3-skew-ps : Skew control of RX data 3 pad 56*4882a593Smuzhiyun - txd0-skew-ps : Skew control of TX data 0 pad 57*4882a593Smuzhiyun - txd1-skew-ps : Skew control of TX data 1 pad 58*4882a593Smuzhiyun - txd2-skew-ps : Skew control of TX data 2 pad 59*4882a593Smuzhiyun - txd3-skew-ps : Skew control of TX data 3 pad 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunKSZ9031: 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun All skew control options are specified in picoseconds. The minimum 64*4882a593Smuzhiyun value is 0, and the maximum is property-dependent. The increment 65*4882a593Smuzhiyun step is 60ps. The default value is the neutral setting, so setting 66*4882a593Smuzhiyun rxc-skew-ps=<0> actually results in -900 picoseconds adjustment. 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun Optional properties: 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun Maximum value of 1860, default value 900: 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun - rxc-skew-ps : Skew control of RX clock pad 73*4882a593Smuzhiyun - txc-skew-ps : Skew control of TX clock pad 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun Maximum value of 900, default value 420: 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun - rxdv-skew-ps : Skew control of RX CTL pad 78*4882a593Smuzhiyun - txen-skew-ps : Skew control of TX CTL pad 79*4882a593Smuzhiyun - rxd0-skew-ps : Skew control of RX data 0 pad 80*4882a593Smuzhiyun - rxd1-skew-ps : Skew control of RX data 1 pad 81*4882a593Smuzhiyun - rxd2-skew-ps : Skew control of RX data 2 pad 82*4882a593Smuzhiyun - rxd3-skew-ps : Skew control of RX data 3 pad 83*4882a593Smuzhiyun - txd0-skew-ps : Skew control of TX data 0 pad 84*4882a593Smuzhiyun - txd1-skew-ps : Skew control of TX data 1 pad 85*4882a593Smuzhiyun - txd2-skew-ps : Skew control of TX data 2 pad 86*4882a593Smuzhiyun - txd3-skew-ps : Skew control of TX data 3 pad 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun - micrel,force-master: 89*4882a593Smuzhiyun Boolean, force phy to master mode. Only set this option if the phy 90*4882a593Smuzhiyun reference clock provided at CLK125_NDO pin is used as MAC reference 91*4882a593Smuzhiyun clock because the clock jitter in slave mode is to high (errata#2). 92*4882a593Smuzhiyun Attention: The link partner must be configurable as slave otherwise 93*4882a593Smuzhiyun no link will be established. 94*4882a593Smuzhiyun 95*4882a593SmuzhiyunKSZ9131: 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun All skew control options are specified in picoseconds. The increment 98*4882a593Smuzhiyun step is 100ps. Unlike KSZ9031, the values represent picoseccond delays. 99*4882a593Smuzhiyun A negative value can be assigned as rxc-skew-psec = <(-100)>;. 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun Optional properties: 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun Range of the value -700 to 2400, default value 0: 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun - rxc-skew-psec : Skew control of RX clock pad 106*4882a593Smuzhiyun - txc-skew-psec : Skew control of TX clock pad 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun Range of the value -700 to 800, default value 0: 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun - rxdv-skew-psec : Skew control of RX CTL pad 111*4882a593Smuzhiyun - txen-skew-psec : Skew control of TX CTL pad 112*4882a593Smuzhiyun - rxd0-skew-psec : Skew control of RX data 0 pad 113*4882a593Smuzhiyun - rxd1-skew-psec : Skew control of RX data 1 pad 114*4882a593Smuzhiyun - rxd2-skew-psec : Skew control of RX data 2 pad 115*4882a593Smuzhiyun - rxd3-skew-psec : Skew control of RX data 3 pad 116*4882a593Smuzhiyun - txd0-skew-psec : Skew control of TX data 0 pad 117*4882a593Smuzhiyun - txd1-skew-psec : Skew control of TX data 1 pad 118*4882a593Smuzhiyun - txd2-skew-psec : Skew control of TX data 2 pad 119*4882a593Smuzhiyun - txd3-skew-psec : Skew control of TX data 3 pad 120*4882a593Smuzhiyun 121*4882a593SmuzhiyunExamples: 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun mdio { 124*4882a593Smuzhiyun phy0: ethernet-phy@0 { 125*4882a593Smuzhiyun rxc-skew-ps = <3000>; 126*4882a593Smuzhiyun rxdv-skew-ps = <0>; 127*4882a593Smuzhiyun txc-skew-ps = <3000>; 128*4882a593Smuzhiyun txen-skew-ps = <0>; 129*4882a593Smuzhiyun reg = <0>; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun ethernet@70000 { 133*4882a593Smuzhiyun phy = <&phy0>; 134*4882a593Smuzhiyun phy-mode = "rgmii-id"; 135*4882a593Smuzhiyun }; 136