1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: MediaTek STAR Ethernet MAC Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Bartosz Golaszewski <bgolaszewski@baylibre.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun This Ethernet MAC is used on the MT8* family of SoCs from MediaTek. 14*4882a593Smuzhiyun It's compliant with 802.3 standards and supports half- and full-duplex 15*4882a593Smuzhiyun modes with flow-control as well as CRC offloading and VLAN tags. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunallOf: 18*4882a593Smuzhiyun - $ref: "ethernet-controller.yaml#" 19*4882a593Smuzhiyun 20*4882a593Smuzhiyunproperties: 21*4882a593Smuzhiyun compatible: 22*4882a593Smuzhiyun enum: 23*4882a593Smuzhiyun - mediatek,mt8516-eth 24*4882a593Smuzhiyun - mediatek,mt8518-eth 25*4882a593Smuzhiyun - mediatek,mt8175-eth 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun maxItems: 1 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun interrupts: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun minItems: 3 35*4882a593Smuzhiyun maxItems: 3 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clock-names: 38*4882a593Smuzhiyun additionalItems: false 39*4882a593Smuzhiyun items: 40*4882a593Smuzhiyun - const: core 41*4882a593Smuzhiyun - const: reg 42*4882a593Smuzhiyun - const: trans 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun mediatek,pericfg: 45*4882a593Smuzhiyun $ref: /schemas/types.yaml#definitions/phandle 46*4882a593Smuzhiyun description: 47*4882a593Smuzhiyun Phandle to the device containing the PERICFG register range. This is used 48*4882a593Smuzhiyun to control the MII mode. 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun mdio: 51*4882a593Smuzhiyun type: object 52*4882a593Smuzhiyun description: 53*4882a593Smuzhiyun Creates and registers an MDIO bus. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyunrequired: 56*4882a593Smuzhiyun - compatible 57*4882a593Smuzhiyun - reg 58*4882a593Smuzhiyun - interrupts 59*4882a593Smuzhiyun - clocks 60*4882a593Smuzhiyun - clock-names 61*4882a593Smuzhiyun - mediatek,pericfg 62*4882a593Smuzhiyun - phy-handle 63*4882a593Smuzhiyun 64*4882a593SmuzhiyununevaluatedProperties: false 65*4882a593Smuzhiyun 66*4882a593Smuzhiyunexamples: 67*4882a593Smuzhiyun - | 68*4882a593Smuzhiyun #include <dt-bindings/interrupt-controller/arm-gic.h> 69*4882a593Smuzhiyun #include <dt-bindings/clock/mt8516-clk.h> 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun ethernet: ethernet@11180000 { 72*4882a593Smuzhiyun compatible = "mediatek,mt8516-eth"; 73*4882a593Smuzhiyun reg = <0x11180000 0x1000>; 74*4882a593Smuzhiyun mediatek,pericfg = <&pericfg>; 75*4882a593Smuzhiyun interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>; 76*4882a593Smuzhiyun clocks = <&topckgen CLK_TOP_RG_ETH>, 77*4882a593Smuzhiyun <&topckgen CLK_TOP_66M_ETH>, 78*4882a593Smuzhiyun <&topckgen CLK_TOP_133M_ETH>; 79*4882a593Smuzhiyun clock-names = "core", "reg", "trans"; 80*4882a593Smuzhiyun phy-handle = <ð_phy>; 81*4882a593Smuzhiyun phy-mode = "rmii"; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun mdio { 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <0>; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun eth_phy: ethernet-phy@0 { 88*4882a593Smuzhiyun reg = <0>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun }; 92