1*4882a593SmuzhiyunProperties for an MDIO bus multiplexer controlled by a memory-mapped device 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is a special case of a MDIO bus multiplexer. A memory-mapped device, 4*4882a593Smuzhiyunlike an FPGA, is used to control which child bus is connected. The mdio-mux 5*4882a593Smuzhiyunnode must be a child of the memory-mapped device. The driver currently only 6*4882a593Smuzhiyunsupports devices with 8, 16 or 32-bit registers. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties in addition to the generic multiplexer properties: 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun- compatible : string, must contain "mdio-mux-mmioreg" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- reg : integer, contains the offset of the register that controls the bus 13*4882a593Smuzhiyun multiplexer. The size field in the 'reg' property is the size of 14*4882a593Smuzhiyun register, and must therefore be 1, 2, or 4. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- mux-mask : integer, contains an eight-bit mask that specifies which 17*4882a593Smuzhiyun bits in the register control the actual bus multiplexer. The 18*4882a593Smuzhiyun 'reg' property of each child mdio-mux node must be constrained by 19*4882a593Smuzhiyun this mask. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunThe FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes. 24*4882a593SmuzhiyunFor the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus. 25*4882a593SmuzhiyunA bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on 26*4882a593SmuzhiyunBRDCFG1 that control the actual mux. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* The FPGA node */ 29*4882a593Smuzhiyun fpga: board-control@3,0 { 30*4882a593Smuzhiyun #address-cells = <1>; 31*4882a593Smuzhiyun #size-cells = <1>; 32*4882a593Smuzhiyun compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; 33*4882a593Smuzhiyun reg = <3 0 0x30>; 34*4882a593Smuzhiyun ranges = <0 3 0 0x30>; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun mdio-mux-emi2 { 37*4882a593Smuzhiyun compatible = "mdio-mux-mmioreg", "mdio-mux"; 38*4882a593Smuzhiyun mdio-parent-bus = <&xmdio0>; 39*4882a593Smuzhiyun #address-cells = <1>; 40*4882a593Smuzhiyun #size-cells = <0>; 41*4882a593Smuzhiyun reg = <9 1>; // BRDCFG1 42*4882a593Smuzhiyun mux-mask = <0x6>; // EMI2 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2) 45*4882a593Smuzhiyun reg = <0>; 46*4882a593Smuzhiyun #address-cells = <1>; 47*4882a593Smuzhiyun #size-cells = <0>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun phy_xgmii_slot1: ethernet-phy@0 { 50*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c45"; 51*4882a593Smuzhiyun reg = <4>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1) 56*4882a593Smuzhiyun reg = <2>; 57*4882a593Smuzhiyun #address-cells = <1>; 58*4882a593Smuzhiyun #size-cells = <0>; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun phy_xgmii_slot2: ethernet-phy@4 { 61*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c45"; 62*4882a593Smuzhiyun reg = <0>; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* The parent MDIO bus. */ 69*4882a593Smuzhiyun xmdio0: mdio@f1000 { 70*4882a593Smuzhiyun #address-cells = <1>; 71*4882a593Smuzhiyun #size-cells = <0>; 72*4882a593Smuzhiyun compatible = "fsl,fman-xmdio"; 73*4882a593Smuzhiyun reg = <0xf1000 0x1000>; 74*4882a593Smuzhiyun interrupts = <100 1 0 0>; 75*4882a593Smuzhiyun }; 76