1*4882a593SmuzhiyunProperties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is a special case of a MDIO bus multiplexer. It allows to choose between 4*4882a593Smuzhiyunthe internal mdio bus leading to the embedded 10/100 PHY or the external 5*4882a593SmuzhiyunMDIO bus. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties in addition to the generic multiplexer properties: 8*4882a593Smuzhiyun- compatible : amlogic,g12a-mdio-mux 9*4882a593Smuzhiyun- reg: physical address and length of the multiplexer/glue registers 10*4882a593Smuzhiyun- clocks: list of clock phandle, one for each entry clock-names. 11*4882a593Smuzhiyun- clock-names: should contain the following: 12*4882a593Smuzhiyun * "pclk" : peripheral clock. 13*4882a593Smuzhiyun * "clkin0" : platform crytal 14*4882a593Smuzhiyun * "clkin1" : SoC 50MHz MPLL 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample : 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunmdio_mux: mdio-multiplexer@4c000 { 19*4882a593Smuzhiyun compatible = "amlogic,g12a-mdio-mux"; 20*4882a593Smuzhiyun reg = <0x0 0x4c000 0x0 0xa4>; 21*4882a593Smuzhiyun clocks = <&clkc CLKID_ETH_PHY>, 22*4882a593Smuzhiyun <&xtal>, 23*4882a593Smuzhiyun <&clkc CLKID_MPLL_5OM>; 24*4882a593Smuzhiyun clock-names = "pclk", "clkin0", "clkin1"; 25*4882a593Smuzhiyun mdio-parent-bus = <&mdio0>; 26*4882a593Smuzhiyun #address-cells = <1>; 27*4882a593Smuzhiyun #size-cells = <0>; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun ext_mdio: mdio@0 { 30*4882a593Smuzhiyun reg = <0>; 31*4882a593Smuzhiyun #address-cells = <1>; 32*4882a593Smuzhiyun #size-cells = <0>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun int_mdio: mdio@1 { 36*4882a593Smuzhiyun reg = <1>; 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <0>; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun internal_ephy: ethernet-phy@8 { 41*4882a593Smuzhiyun compatible = "ethernet-phy-id0180.3301", 42*4882a593Smuzhiyun "ethernet-phy-ieee802.3-c22"; 43*4882a593Smuzhiyun interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 44*4882a593Smuzhiyun reg = <8>; 45*4882a593Smuzhiyun max-speed = <100>; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun}; 49